Simulation of 2-bit SONOS Nonvolatile Semiconductor Memory Cell

Characterizing damage to ONO dielectrics induced during programming SONOS/NROM TM non-volatile semiconductor memory (NVSM) devices

The nonvolatile and volatile memory characteristics of feedback field-effect transistors (FBFETs) with nitride charge storage layers were theoretically studied. Because of the electrons and holes stored in the nitride layer, the threshold voltage (V TH) window of 0.6 V was opened/observed. And, with the help of the formation of a positive feedback loop in the p+–n+–p–n+ doped silicon region in FBFET, it turned out that the read delay time of the FBFET for nonvolatile memory applications can be shorter than 1 ns. On the other hand, for the volatile memory applications, the FBFET can implement (a) non-destructive read operations owing to the self-sustaining feedback loop characteristic, and (b) a significantly long retention time which can suppress the power dissipation in refresh. Furthermore, the operation scheme of volatile memory mode can be simplified by setting gate voltage conditions for the hold and read operations to be identical to each other. The FBFET showed its on-state drive current of 6 × 10−5 A μm−1 and the on-/off-current ratio of 109. The potential of merging nonvolatile and volatile memory devices in a single cell is discussed and demonstrated in this work.

Non-volatile memory is approaching its fundamental limits with the Si3N4 storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd2O3 storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO2 storage layer. Yttrium doping increases the storage window of the BaTiO3 storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

The effects of nitrided SiO2/Si(100) interfaces upon cycling endurance in silicon–oxide–nitride–oxide–silicon (SONOS) nonvolatile memory transistors are investigated. Analysis of metal–oxide–silicon field-effect transistor subthreshold characteristics indicate cycling degradation to be a manifestation of interface trap generation at the tunnel oxide/silicon interface. After 106 write/erase cycles, SONOS film stacks prepared with nitrided tunnel oxides exhibit enhanced cycling endurance over stacks prepared with non-nitrided tunnel oxides. If the capping oxide is formed by steam oxidation, rather than by deposition, SONOS stacks prepared with non-nitrided tunnel oxides exhibit endurance characteristics similar to stacks with nitrided tunnel oxides. For this case, a mechanism for latent nitridation of the tunnel oxide/silicon interface is proposed.

Modeling of interface trap charges induced degradation in underlap DG and GAA MOSFETs

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) based nonvolatile memory has emerged as the most mature nonvolatile semiconductor memory (NVSM) currently in use for space applications. SONOS 64k EEPROMs have been flying in numerous satellite applications since 1992 with a 256k EEPROM version of this part qualified for space applications in 2000. This paper summarizes the production and development status of a family of SONGS-based devices (EEPROMs, FPGAs, Controller ASICs) currently being manufactured at the Northrop Grumman Corporation (NGC) Advanced Technology Laboratories in Baltimore, Maryland.

Strained-Si technology could enhance the carrier mobility and improve the device performance. Contact-etch-stop-layer (CESL) structure with different stress and SiGe channel was fabricated with 90-nm technology. The electrical properties of N and PMOSFET devices combining CESL and SiGe channel were investigated. The short channel effects (SCE), such as drain-induced barrier lowering (DIBL), were also studied. Moreover, the stress contour in the SiGe channel has been simulated with TCAD to understand the relationship between stress distribution and device performance for different CESL structures. It is observed that the stress in the channel region was independent of the type of N or PMOSFET devices, but it was dependent on the CESL type and channel length. Based on the experimental and simulation results, it is confirmed that the device performance is associated with the stress in the channel, and the approach of CESL stressor and SiGe channel is shown to effectively improve the mobility of NMOSFETs and PMOSFETs.

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

A study on the improved programming characteristics of flash memory with Si 3N 4/SiO 2 stacked tunneling dielectric

Gadolinium-based metal oxide for nonvolatile memory applications

A novel electrically erasable programmable logic device (EEPLD) memory cell with new program and erase operations fabricated by a standard complementary metal–oxide–semiconductor (CMOS) logic process is presented. The cell which consists of two metal–oxide–semiconductor field effect transistor (MOSFET) transistors in series is programmed by select-gate-controlled drain avalanche hot hole injection and erased by channel hot electron injection. The cell exhibits good programming and erasing characteristics along with endurance up to 105 cycles, and 1000 h of data retention at 150°C. A new self-converged programming scheme is investigated for multilevel or analog storage. Without a P-well or an N-well serving as a coupling gate, the novel cell provides the smallest area size per bit reported for a single-poly nonvolatile memory. With its small cell size and full compatibility with the standard CMOS logic process, the novel EEPLD can be easily adopted in highly integrated VLSI systems.

The nonvolatile memory (NVM) concept based on the injection and storage of charges in the floating-gate (FG) of a MISFET device was introduced in 1967 (Kahng 1967). Since then, this kind of memory device has evolved utilizing advances in material technology and device design (Groeseneken 1997; Fazio 2004), leading to the Flash memories, which are the prevailing NVM technology at present (see Chap. 1). The latter become a significant part of the semiconductor market especially in the last decade as a result of the rapid market expansion of the portable systems (Lu 2010). Introduced also in the late sixties, the “charge trap” (CT) memory refers to a device structure and operating principles similar to those of a FG memory. The main difference between these two kinds of NVMs is that the charges are stored in a conducting material (usually a doped polysilicon layer) in the case of the FG memories, while for the CT memories charge storage takes place in localized traps within a dielectric layer (typically made of silicon nitride). As recalled in Sect. 3.2 of this chapter, the CT memories have been the focus of intense research and product development since the early demonstration of MNOS devices. In recent years, they benefited from remarkable advances in thin film technology and charge-trap engineering, which have increased their potential to move from niche applications (e.g., smartcards, specific space and military systems) to mass applications guided today by the growing demands of the portable market. The conventional FG memories, despite their leading role in NVMs, are facing a number of challenges as scaling continues beyond the 22 nm technology node (to date at 19–16 nm, third Q 2014). Severe issues are the floating-gate interference effect between adjacent memory cells, the patterning costs and the reduction of the tunnel oxide thickness (Mark 2013; Libsch and White 1990). Compared to the FG memories, the advantages of the CT memories in terms of scalability and fabrication requirements (and thus in production costs) make them particularly attractive for the further development of ultra-scaled NVMs for both standalone and embedded applications. In addition to the brief historical outline and state of the art of the CT memories presented in Sect. 3.2, two technological options related to the use of the low-energy (LE) Si ion-implantation technique for achieving improved CT memories are described in Sects. 3.3 and 3.4. Section 3.3 reports on the development of CT devices using a nitride layer with an embedded thin band of Si nanoparticles, while Sect. 3.4 deals with CT devices employing a control oxide layer obtained by low-temperature oxidation of LE Si-implanted nitride film. These technological options are part of our investigations we conducted the last 20 years in the field of NVMs.

Hardware specialization is commonly used in data-centers to ameliorate the nearing end of CMOS technology scaling. While offering superior performance and energy-efficiency returns compared to general-purpose processors, specialized accelerators are bound to the same device technology constraints, and are thus prone to similar limitations in the future. Once technology scaling plateaus, accelerator and application tuning will reach a point of near-optimum, with no clear direction for further improvements. Emerging non-volatile memory (NVM) technologies follow different scaling trends due to different physical properties and manufacturing techniques. NVMs have inspired recent efforts of innovation in computer systems, as they possess appealing qualities such as high capacity and low energy. We present the COmpute-REuse Accelerators (COREx) architecture that shifts computations from the scalability-hindered transistor-based logic towards the continuing-to-scale storage domain. COREx leverages datacenter redundancy by integrating a storage layer together with the accelerator processing layer. The added layer stores the outcomes of previous accelerated computations. The previously computed results are reused in the case of recurring computations, thus eliminating the need to re-compute them. We designed COREx as a combination of an accelerator and specialized storage layer using emerging memory technologies, and evaluated it on a set of datacenter workloads. Our results show that, when integrated with a well-tuned accelerator, COREx achieves an average speedup of 6.4X and average savings of 50% in energy and 68% in energy-delay product. We expect further increase in gains in the future, as memory technologies continue to improve steadily.

In this work, we present the first implementation of spike-timing-dependent plasticity (STDP) and unsupervised learning in a mainstream NOR Flash memory array based on floating-gate cells. A simple yet effective word-line and bit-line pulse scheme is proposed to make a common-ground double-polysilicon NOR array in 40 nm embedded technology work as an artificial synaptic array in a spiking neural network learning according to the STDP rule, with no change required either to the array or to the cell design. With this scheme, long-term potentiation and long-term depression of the synaptic weights are achieved, respectively, by hot-hole injection and channel hot-electron injection at the drain side of the cells. Unsupervised learning is experimentally demonstrated in the array, paving the way for the development of large-scale and high-density neuromorphic systems based on mainstream nonvolatile memory technologies.

The reliability performance of a 64 K flash memory based on a single-transistor, floating-gate memory cell is considered. The reliability performance of these memories, before program/erase cycling, matches that of UV EPROMs. Cycling generally does not introduce defect-related failures common to some EEPROMs. However, it may aggravate two intrinsic instabilities found in the UV EPROM (intrinsic charge loss and the DC program disturb mechanism). Experience shows that these are related effects caused by injection of holes during the erase step of the cycle. High source-to-substrate electric fields, during erase, generate these holes. Channel hot electron injection, for programming, plays no significant role in the observed degradation. These cycling effects can be addressed through incorporation of additional margin into the flash cell. Through such cell optimization, the reliability of these memories is made equivalent to that of conventional UV EPROMs, even after hundreds of program/erase cycles. >