Simulation of single-event upset in power MOSFETs

Analysis techniques on a 90 nm deep trench capacitor have provided the physical evidence for a heavy ion induced single event gate rupture (SEGR). The trench capacitor is from a 90 nm bulk complementary metal oxide semiconductor technology and is used for the reduction of single event upsets. SEGR damaged trench oxides are identified via a voltage contrast technique using a focused ion beam. The focused ion beam was used to delayer and expose the deep trenches. A wet chemical etch was used to identify the location of the SEGR leakage path. The oxide rupture location was observed at the top of the deep trench capacitor.

The effects of heavy-ion test conditions and beam energy on device response are investigated. These effects are illustrated with two types of test vehicles: SRAMs and power MOSFETs. In addition, GEANT4 simulations have also been performed to better understand the results. Testing to high fluence levels is required to detect rare events. This increases the probability of nuclear interactions. This is typically the case for power MOSFETs, which are tested at high fluences for single event burnout or gate rupture detection, and for single-event-upset (SEU) measurement in SRAMs below the direct ionization threshold. Differences between various test conditions (e.g., “in air” or vacuum irradiations, with or without degraders) are also explored. Nuclear interactions with any materials in the beam's path can increase the number of high collected charge events potentially impacting the experimental results. A “species” effect has been observed in the power MOSFET devices examined in this work. When the beam energy increases, the single-event-burnout (SEB) voltage is constant, such that the SEB voltage is determined only by the species of the ion beam. The species effect is shown to be due to high collected charge events induced by nuclear interactions, which can lead to premature SEB. If a device is sensitive to the species effect, the worst-case test conditions will be for the heaviest ion species, which can produce the largest linear-energy-transfer (LET) secondaries. SRAMs can also be sensitive to the species effect below the direct ionization threshold LET. For the devices used in this work, the worst-case energy for SEU characterization is <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim 10'{\rm s}~{\rm MeV/u}$</tex> </formula> where the species dominates the device response. In the 10's MeV/u range the heaviest species result in the largest cross sections. However, at very high energies (100's MeV/u), the species is not the dominant parameter because of differences in the population of secondaries created by nuclear interactions. At very high energies the SEU cross section below the direct ionization threshold LET decreases by several orders of magnitude compared to 10's MeV/u SEU data. The results of this work emphasize that there is no such thing as an “ideal” test facility. Nevertheless, these results can be used by experimenters to optimize the integrity of their results for given test conditions.

The heavy-ion fluence required to induce Single-Event Gate Rupture (SEGR) in power MOSFETs is measured as a function of the drain bias, V/sub DS/, and as a function of the gate bias, V/sub GS/. These experiments reveal the abrupt nature of the SEGR-voltage threshold. In addition, the concepts of cross-section, threshold, and saturation in the SEGR phenomenon are introduced. This experimental technique provides a convenient method to quantify heavy-ion effects in power MOSFETs.

The results of recent Single Event Gate Rupture and Single Event Burnout testing on power MOSFETS are presented. The recent test data show a considerable drop in failure voltage in comparison to manufacturer data for device ratings over 130V. The effect of range is considered to account for this difference. The methods and practices for testing and data analyses that need to be used for adequate SEE testing of power MOSFETs are also presented. I. INTRODUCTION any space applications are demanding more power and higher voltages. Unfortunately, the technology behind high blocking voltages in discrete devices is susceptible to radiation effects. The large feature sizes and low-doped regions of silicon are the underlying liable areas of these devices to radiation. The application of power devices can be especially stressful when power or voltage requirements are demanding, or the mission environment is hostile. Most power solutions for design approaches in space employ the vertical power MOSFET, but these devices present limitations and trade challenges to projects that require high speed or very large power for high current applications. This work presents the results from various testing of power MOSFETs with rigorous test conditions. This study aims to refine the methodology for adequate hardness assurance of power MOSFETs for space missions.

Neutron test campaigns on silicon (Si) and silicon carbide (SiC) power MOSFETs and IGBTs were conducted at the TRIGA (Training, Research, Isotopes, General Atomics) Mark II (Pavia, Italy) nuclear reactor and ChipIr-ISIS Neutron and Muon Source (Didcot, U.K.) facility. About 2000 power transistors made by STMicroelectronics were tested in all the experiments. Tests with thermal and fast neutrons (up to about 10 MeV) at the TRIGA Mark II reactor showed that single-event burnout (SEB) failures only occurred at voltages close to the rated drain-source voltage. Thermal neutrons did not induce SEB, nor degradation in the electrical parameters of the devices. SEB failures during testing at ChipIr with ultra-fast neutrons (1-800 MeV) were evaluated in terms of failure in time (FIT) versus derating voltage curves according to the JEP151 procedure of the Joint Electron Device Engineering Council (JEDEC). These curves, even if scaled with die size and avalanche voltage, were strongly linked to the technological processes of the devices, although a common trend was observed that highlighted commonalities among the failures of different types of MOSFETs. In both experiments, we observed only SEB failures without single-event gate rupture (SEGR) during the tests. None of the power devices that survived the neutron tests were degraded in their electrical performances. A study of the worst-case bias condition (gate and/or drain) during irradiation was performed.

A power MOSFET suitable for synchronous rectification in 1-10 MHz switching power supplies is presented. Three device structures are compared to find the lowest on-state resistance, off-state capacitance product. The lightly doped drain region typical of most power MOSFETs is removed to give a body diode with a 1 ns reverse recovery time. Both of these types are needed for efficient operation at high frequencies. Process details and experimental results are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The leakage currents through the gate oxide of MOS capacitors fabricated on n-type 4H-Silicon Carbide (SiC) was measured under accumulation bias conditions with heavy-ion irradiation. The Linear Energy Transfer (LET) dependence of the critical electric field (Ecr) at which dielectric breakdown occurred in these capacitors with two different oxide thicknesses was evaluated. The MOS capacitors with thin gate oxide showed higher Ecr values than those with thick gate oxide. The linear relationship between the reciprocal Ecr and LET was observed for both MOS capacitors. The slope of LET dependence of 1/Ecr for SiC MOS capacitors was smaller than that for Si, suggesting that SiC MOS devices are less susceptible to single-event gate rupture (SEGR) than Si MOS devices.

Robustness and reliability review of Si and SiC FET devices for more-electric-aircraft applications

A Uni-gate vertical power MOSFET with improved figure of Merits: Design and analysis

The gate oxide layer and parasitic bipolar junction transistor are inherent elements of vertical double-diffused power metal–oxide–semiconductor field-effect transistors (MOSFETs). Single-event gate rupture (SEGR) and single-event burnout (SEB) may be triggered by penetration of energetic ions through sensitive regions of such MOSFET devices when used in space environments. Based on the recombination mechanism in a heavily doped P+ buried layer and the higher breakdown voltage when using a thick oxide layer, a new structure for power MOSFETs that are irradiation hardened against SEGR and SEB was developed in this work, based on three typical characteristics: an N+ buried layer, a P+ buried layer, and a thick oxide above the neck. The results reveal that the safe operation region of such an N-channel power MOSFET in a single-event irradiation environment is enhanced by 300 % for a linear energy transfer value of 98 MeV cm2/mg. Such structures could be widely used when designing single-event irradiation-hardened power MOSFETs.

The effect of static charge imbalance on the forward blocking voltage (FBV) of a superjunction power MOSFET designed for 600 V is investigated with device simulation. It is observed that the presence of the conduction channel and carriers in the drift region in the on state effectively changes the charge balance in the device. As a result, the BV changes substantially with the applied gate voltage. The variation of FBV as function of gate voltage V/sub GS/ is obtained by device simulation, for three cases of superjunction (SJ) drift layer doping variations (i) N/sub a/ = N/sub d/, (ii) N/sub a/ > N/sub d/, (iii) N/sub d/ > N/sub a/. Representative potential contours are also shown for illustration.

In the automotive industry, there is a strong trend that has increased the electronics in cars for various functions like fuel injection, electric control of doors and windows, electric chair adjustment, air conditioning etc. The 12V battery used in the present cars will not be sufficient for the increasing number of functions, as a consequence, a change towards 42V batteries will be necessary. For these automotive systems, so called smart power ICs must be used. These are the chips in which the power functionality e.g. control of motor is integrated with logic control. There is also a trend towards operation at high voltages and integrating more intelligence using a microcontroller's RAM/ROM memory and several other sensors and interfaces. The final goal is the integration of a complete system on a single chip, so called power system on chip (SoC). The interest in accurate modeling of high voltage transistors has increased in recent years due to the compatibility of these devices with standard CMOS technology. However, existing LDMOS models are not accurate enough for this task and SPICE models are specially weak for AC performance. The limitation of these models lies in their lack of capability to physically model some of the characteristic phenomena observed in high voltage devices. The increased difficulty is related to complex 2D effects specific to asymmetric high voltage device architectures. This thesis presents the compact modeling of high voltage devices. First, a highly scalable general high voltage MOSFET model, for the first time, is presented, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented in Verilog-A code and tested on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The model exhibits excellent scalability with transistor width, drift length, number of fingers and temperature. Second, the compact modeling of lateral non-uniform doping is presented, which has great impact on the AC behavior. Third, the invalidity of Ward-Dutton charge partitioning scheme for lateral non-uniformly doped MOSFET is explained. A novel partitioning scheme is then developed and validated on the device simulation. For the first time, noise modeling of lateral non-uniformly doped MOSFET is carried out and validated on the device simulation.

Failure modes on low voltage power MOSFETs under high temperature application

Shielded-Gate Trench MOSFET (SGT MOSFET) complies with two-dimensional charge balance principle. SGT MOSFETs improve the performance of medium and low voltage power MOSFET. There is a shielded gate in the drift region, which provides SGT MOSFET a significant advantage in terms of specific on-resistance RON(SP) and figure of merit (FOM= Ron*Qg). SGT MOSFET has the advantages of low specific on resistance, fast switching speed, low switching loss and simple driving <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]-[3]</sup> .The process of SGT MOSFET is so complex, including more than six times of photoetchings, and several times of insulating oxide layer growth. This leads to thin dielectric layers and complex structures.At the end of process of SFG MOSFET, wire bonding of source is on the aluminum layer above the oxide layers and Gate, which is thin and has low mechanical strength. And it is also the key technology to realize electronic interconnection. Therefore, wire bonding is one of the most difficult and key processes in the packaging process. Failure caused by wire bonding false accounts for about 25% of the whole chip failure. What’s worse is that the chips failed caused by poor wire bonding is often in batches, which will cause great loss to the user and relevant parties. With the development of chip miniaturization, there are also circuit module and functional structures under the bonding PAD. There are oxidizing materials between bonding PAD and functional structure, to realize circuit insulation. The oxidizing material is often too thin to preserve adequate strength, which puts engineers into a dilemma, because it is a big challenge for bonding process control. If the bonding process parameter is not selected properly, the chip may work abnormally. Insufficient bonding strength may lead to poor electrical connection, such as excessive contact resistance. Excess bonding force may cause damage and fracture. The oxidizing material under bonding PAD may be damaged, or chip structure may be damaged, which will cause slight internal leakage, and function of the appliance may be lost. Unfortunately, these defects are unstable and occasional, and they can’t be detected by the packaging factory one hundred percent immediately. Then great loss may be caused to users by these defects <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4]-[6]</sup> .However, at present, few cases of failure caused by process defects are published. In this paper, a failed SGT MOSFET was analyzed. Slight leakage current was found between Gate and Source, and function of the SGT MOSFET was lost. No obvious defects or abnormality were found in the SGT MOSFET after it was de-capped. Optical Beam Induced Resistance Change (OBIRCH) was used to check out the possible defects. Something abnormal was found under the bonding area. And then Focused Ion beam (FIB) was used to make micro-section to show the suspicious point. Cracks and holes in oxidizing material were found. There were cracks in the Source metal layer of the cell, and some cracks extend to the Gate of MOSFET, resulting in leakage between Gate and Source poles.SGT MOSFET failed because of poor process quality. Thus, the way to improve quality of SGT MOSFET is to improve oxide layers and reduce bonding pressure. Field oxide layer growth process should be Improved to avoid cracks and holes. Parameter setting and consistency of bonding wire process is also a crucial factor.

A novel two-dimensional (2D) process simulator has been developed which can handle local oxidation, implantation through arbitrary mask edges, nonplanar surfaces, and high concentration diffusion. Through coupling of 2D process and device simulators, the sensitivity of perimeter junction capacitance and breakdown voltage to variations in boron channel-stop implantation dose and local oxidation time has been simulated for a standard NMOS technology. Experimental results using test structures have confirmed the simulations. It is shown that simple power-law dependencies as a function of the process variables give good agreement with the data.