Simultaneous WRITES of parallel random access machines do not help to compute simple arithmetic functions

Two adaptive, level-order tree traversal algorithms are proposed for an exclusive-read and exclusive-write (EREW), parallel random access machine (PRAM) model of computation. Our breadth-first traversal algorithm for a general tree with n nodes achieves O((n/p)*log n /log(n/p)) time complexity using p processors on the EREW model, and hence it attains optimal speedup for p ≤ n1 − e, where 0 < e ≤ 1. This algorithm performs better (in terms of processor-time product) than an existing algorithm [12] which has O(k log n) time complexity using O(n1 + 1/k) processors on a concurrent-read and exclusive-write (CREW), PRAM model. The proposed breadth-depth algorithm for traversing a general tree requires O(n/p + log n) time on the EREW model, and thus it achieves optimal speedup for p ≤ n/log n. This algorithm provides a significant improvement over an existing parallel breadth-depth algorithm [4] which requires O(log n) time with O(n2) processors on CREW model. Our breadth-first traversal algorithm uses an Euler tour technique [20], and a list construction technique which is similar to the one used in [18] for solving the adjacency list construction problem for graphs. The breadth-depth traversal algorithm, on the other hand, is based on a special characterization which enables the reduction of this problem into a variety of list ranking problems.

In this paper, the problem of A-order of binary tree is studied with the PRAM(Parallel Random Access Machine) model of parallel computation and a parallel algorithm for A-order of binary tree is proposed. The process of the parallel algorithm is proceed with detailed description and verified analysis with an application instance. The parallel algorithm of A-order of binary tree provides using and reference for applying it to binary tree traverse sequence and solving the parallelism problem of application program.

Efficient parallel factorization and solution of structured and unstructured linear systems

We present a new programming language designed to allow the convenient expression of algorithms for a parallel random access machine (PRAM). The language attempts to satisfy two potentially conflicting goals: On the one hand, it should be simple and clear enough to serve as a vehicle for human-to-human communication of algorithmic ideas. On the other hand, it should be automatically translatable to efficient machine (i.e., PRAM) code, and it should allow precise statements to be made about the amount of resources (primarily time) consumed by a given program. In the sequential setting, both objectives are reasonably well met by the Algol-like languages, e.g., with the RAM as the underlying machine model, but we are not aware of any language that allows a satisfactory expression of typical PRAM algorithms. Our contribution should be seen as a modest attempt to fill this gap.

We consider parallel algorithms working in sequential global time, for example, circuits or parallel random access machines (PRAMs). Parallel abstract state machines (parallel ASMs) are such parallel algorithms, and the parallel ASM thesis asserts that every parallel algorithm is behaviorally equivalent to a parallel ASM. In an earlier article, we axiomatized parallel algorithms, proved the ASM thesis, and proved that every parallel ASM satisfies the axioms. It turned out that we were too timid in formulating the axioms; they did not allow a parallel algorithm to create components on the fly. This restriction did not hinder us from proving that the usual parallel models, like circuits or PRAMs or even alternating Turing machines, satisfy the postulates. But it resulted in an error in our attempt to prove that parallel ASMs always satisfy the postulates. To correct the error, we liberalize our axioms and allow on-the-fly creation of new parallel components. We believe that the improved axioms accurately express what parallel algorithms ought to be. We prove the parallel thesis for the new, corrected notion of parallel algorithms, and we check that parallel ASMs satisfy the new axioms.

We prove that every unambiguous context-free language can be recognized in O(log n) time on a parallel random access machine (P-RAM). This strengthens the result of Reif [2], who has proved that every deterministic context-free language can be recognized in O(log n) time on a P-RAM.

In the spirit of A. Cobham's algebraic, machine-independent characterization of the collection FP of polynomial time computable functions in [Cob65] (see also [Ros84]), we characterize the collection AC O of functions computable with uniform constant depth polynomial size circuits and the collection NC of functions computable in polylogarithmic time with a polynomial number of processors on a parallel random access machine (PRAM). From these characterizations, we obtain level-by-level characterizations of the intermediate classes AC k and NC k . The class AC O is the closure of certain simple initial functions under composition and a variant of bounded primitive recursion called concatenation recursion on notation. The class NC is obtained from the same initial functions by adding a second variant of bounded primitive recursion called weak bounded recursion on notation. Thus, well known parallel complexity classes are characterized in a machine-independent manner using sequential operations. As a corollary, one can give Backus-Naur for a sequential programming language fragment of Pascal which "captures" the parallel complexity class NC, in the sense that functions, which can be programmed in this fragment, are exactly those which are computable in polylogarithmic time with a polynomial number of processors on a PRAM Note that this latter result is much more than a simple serialization of parallel code.

Dear SCPE Reader, We present a selection of papers which are extensions of papers presented at the 7-th International Symposium on Parallel and Distributed Computing, 1–5 July 2008, in Krakow, Poland. The motivation for publishing the selection in the SCPE Journal was, on the one hand, to present the flavour of the research reported at the conference and on the other hand to present some of the most relevant topics currently focused on the research on parallel and distributed computing in general. The selection contains only 6 papers out of about 60 presented at the conference, and thus, is far from covering all relevant topics represented at the ISPDC 2008. This is because not all of the invited authors were patient enough to accept a fairly long paper publishing process. Nevertheless, we hope that the presented papers will bring you closer to the research covered by the ISPDC conferences and will encourage you to participate in future ISPDC editions. The first paper ``The Impact of Workload Variability on Load Balancing Algorithms'' is by Marta Beltran and Antonio Guzman from King Juan Carlos University in Spain. It concerns an important topic of load balancing in cluster systems, namely adaptativity of the load balancing algorithms to changes of the workload in the system. Adequate accounting for additional load in the hosting system is of great relevance for correct optimization effects. The paper presents a thorough formal analysis of the workload variability metrics and their influence on the quality of load balancing algorithms. Four basic activities appearing in load balancing algorithms are identified, and based on them some algorithmic solutions are proposed to correctly deal with workload variability in system load balancing. The problem of dynamic load balancing algorithms robustness has been discussed. Two different robustness metrics sensitive to the applied type of opimization: local task-oriented or a global one enable selecting task remote execution or migration as load balancing operations. The proposed approach is illustrated with experiments. The second paper ``Model-Driven Engineering and Formal Validation of High-Performance Embedded Systems'' is by Abdoulaye Gamatie, Eric Rutten, Huafeng Yu, Pierre Boulet, Jean-Luc Dekeyser, from University of Lille and INRIA in France. The paper is concerned with a very advanced methodology of designing correct parallel embedded systems for intensive data-parallel computing. In their previous research, the authors of the paper designed the GASPARD embedded system design framework. It is based on the hardware/software co-design approach through model-driven engineering. The framework is based on an UML-like model specification language in which hardware and software elements are modelled using a component approach with special mechanisms for repetitive structures. This paper tries to combine the modelling framework of GASPARD with the mechanisms of synchronous languages to achieve design verifiability provided for such languages. The paper shows how GASPARD models can be translated into synchronous models based on data flow equations in order to formally check their correctness. The proposed approach is illustrated with an example of a video processing system. The third paper ``Relations Between Several Parallel Computational Models'' is by Stephan Bruda and Yuanqiao Zhang from Bishop’s University in Canada. The paper is concerned with theoretical aspects of shared memory systems described by the parallel random access machine PRAM model and aims in studying performance properties of different types of PRAM systems. The attention is focussed on analysing the computational power of two more sophisticated PRAM models (Combining CRCW and Broadcast Selective Reduction), which include data reduction in case of concurrent writes. The paper shows that these two models have equivalent computational power, which is a new result comparing the existing literature. The performance of both models applied to reconfigurable multiple bus machines was studied as a possible architectural solution for current VLSI processor implementations. It was shown that in such systems under reasonable assumptions concurrent-write does not enhance performance comparing the exclusive-write model. Another result important for the VLSI technology is that the Combining CRCW PRAM model (in which data of concurrent writes are arthmetically or logically combined before write) and the exclusive-write on directed reconfigurable busses perform in equivalent way under strong real-time requirements. The fourth paper ``Experiences with Mesh-Like Computations Using Prediction Binary Trees'' is by Gennaro Cordasco, Biagio Cosenza, Rosario de Chiara, Ugo Erra and Vittorio Scarano from the University ``degli Studi'' of Salerno and the University ``degli Studi della Biasilicata'' of Potenza in Italy. The paper concerns optimization methods for mesh-like computations in clusters of processors. The computations are perfomed assuming a phase-like program execution control using a tiling approach which reduces inter-processor communication. A temporal coherence is also assumed, which means that task sizes provide similar execution times in consecutive phases. Temporary coherent computations are structured in a Prediction Binary Tree, in which leaves represent computing tiles to be mapped to processors. A phase-by-phase semi-static load balancing is introduced to the scheduling algorithm. The scheduling algorithm is equipped with a predictor, which estimates the computation time of next phase tiles based on previous execution times and modifies the tiles to achieve balanced execution in phases. For this, two heuristics are used to leverage on data locality in processors. The proposed approach is illustrated by the example of interactive rendering with Parallel Ray Tracing algorithm. The fifth paper ``The Influence of the IBM pSeries Servers Virtualization Mechanism on Dynamic Resource Allocation in AIX 5L'' is by Maciej Mlynski from ASpartner Limited in Poland. The paper concerns a very up-to-date problem of system virtualization and presents the results of research carried on IBM pSeries servers. IBM is strongly developing the virtualization technique especially on IBM pSeries servers enabling an improved and flexible sharing of system resources between applications. The paper investigates novel facilities for dynamic resource management such as micro-partitioning and partition load manager. They enable dynamic creation of workload logical partitions of system resources and their dynamic mangement. It includes run-time resource re-alocation between logical partitions including setting of sharing specifications as well as run-time adding/removing/setting parameters of resources in the system. It remains an open question how to properly tune parameters of the operating system using the provided virtualization facilities to obtain the best efficiency for a given application program. The paper presents the results of experiments which study the effects of tuning the disk subsystem parameters under the IBM AIX 5L operating system with the use of the provided virtualization facilities on the resulting application execution performance. The results show that even small deterioration in the resource pool status requires an immediate adaptation of the operating system parameters to maintain the required performance. The sixth paper ``HeteroPBLAS: A Set of Parallel Basic Linear Algebra Subprograms Optimized for Heterogeneous Computational Clusters'' is by Ravi Reddy, Alexey Lastovetsky and Pedro Alonso from University College Dublin in Ireland and Polytechnic University of Valencia in Spain. The paper concerns the methodology for parallelization of linear algebra computations for execution in heterogeneous cluster environments. The design of the HeteroPBLAS library (Parallel Basic Linear Algebra Subprograms) for heterogeneous computational clusters is presented. The main contribution of the paper is the automation of the parallelization and optimization of the PBLAS, which is done by means of a special user interface and the underlying set of functions. An important element is here a performance model that is based on program code instrumentation, which determines parameters of the application and the executive heterogeneous platform relevant for execution performance of parallel code. The parameter values specified for or returned by execution of the performance model functions are next used for generation and optimal mapping of the parallel code of the library subroutines. The proposed approach is illustrated by experimental results of execution of optimized HeteroPBLAS programs on homogeneous and heterogeneous computing clusters. Marek Tudruj

The fastest deterministic algorithms for connected components take logarithmic time and perform superlinear work on a Parallel Random Access Machine (PRAM). These algorithms maintain a spanning forest by merging and compressing trees, which requires pointer-chasing operations that increase memory access latency and are limited to shared-memory systems. Many of these PRAM algorithms are also very complicated to implement. Another popular method is “leader-contraction” where the challenge is to select a constant fraction of leaders that are adjacent to a constant fraction of non-leaders with high probability, but this can require adding more edges than were in the original graph. Instead we investigate label propagation because it is deterministic, easy to implement, and does not rely on pointer-chasing. Label propagation exchanges representative labels within a component using simple graph traversal, but it is inherently difficult to complete in a sublinear number of steps. We are able to overcome the problems with label propagation for graph connectivity. We introduce a surprisingly simple framework for deterministic, undirected graph connectivity using label propagation that is easily adaptable to many computational models. It achieves logarithmic convergence independently of the number of processors and without increasing the edge count. We employ a novel method of propagating directed edges in alternating direction while performing minimum reduction on vertex labels. We present new algorithms in PRAM, Stream, and MapReduce. Given a simple, undirected graph [Formula: see text] with [Formula: see text] vertices, [Formula: see text] edges, our approach takes O(m) work each step, but we can only prove logarithmic convergence on a path graph. It was conjectured by Liu and Tarjan (2019) to take [Formula: see text] steps or possibly [Formula: see text] steps. Our experiments on a range of difficult graphs also suggest logarithmic convergence. We leave the proof of convergence as an open problem.

In this paper we prove lower bounds on the computational complexity of symmetric functions on parallel machines. The parallel models considered are PRIORITY and ARBITRARY, both widely used versions of the Parallel Random Access Machine (PRAM). We first consider PRIORITY. We prove that a PRIORITY PRAM with one shared memory cell and O(n) processors requires Ω(g(n)) time in order to decide if a binary vector of length n has at least g(n) 1's, for the case g(n)=o(n1/4). This is the decision problem for the threshold language Lg. Our lower bound is tight. For PRIORITY with m shared memory cells we prove an Ω(g(n)/m) lower bound. The limitation on the number of processors is essential, since with enough processors Lg can be decided by the same model in O(√g(n)) time. The limitation on g is important: for instance, for g(n)=n/2 Lg can be decided in time O(√g(n)), which is optimal [VW].

This paper introduces a novel parallel data structure called the recursive star-tree (denoted “${}^ * $-tree”). For its definition a generalization of the $ * $ functional is used (where for a function $f * f(n) = \min \{ {i|f^{(i)} (n) \leqslant 1} \}$ and $f^{(i)} $ is the ith iterate of f). Recursive ${}^ * $-trees are derived by using recursion in the spirit of the inverse Ackermann function. The recursive ${}^ * $-tree data structure leads to a new design paradigm for parallel algorithms. This paradigm allows for extremely fast parallel computations, specifically, $O(\alpha (n))$ time (where $\alpha (n)$ is the inverse of the Ackermann function), using an optimal number of processors on the (weakest) concurrent-read, concurrent-write parallel random-access machine (CRCW PRAM). These computations need only constant time, and use an optimal number of processors if the following nonstandard assumption about the model of parallel computation is added to the CRCW PRAM: an extremely small number of processors each can write simultaneously into different bits of the same word. Applications include finding lowest common ancestors in trees by a new algorithm that is considerably simpler than the known algorithms for the problem, restricted domain merging, parentheses matching, and a new parallel reducibility.

This paper resolves a long-standing open problem on whether the concurrent write capability of parallel random access machine (PRAM) is essential for solving fundamental graph problems like connected components and minimum spanning trees in O (log n ) time. Specifically, we present a new algorithm to solve these problems in O (log n ) time using a linear number of processors on the exclusive-read exclusive-write PRAM. The logarithmic time bound is actually optimal since it is well known that even computing the “OR” of n bit requires Ω(log n time on the exclusive-write PRAM. The efficiency achieved by the new algorithm is based on a new schedule which can exploit a high degree of parallelism.

Simulating the CRCW PRAM on reconfigurable networks

The authors propose a novel framework for designing efficient parallel algorithms on series parallel graphs. Recently, a novel approach for recognizing series parallel graphs was presented by D. Eppstein. Eppstein explored characterizations of the ear decomposition of series parallel graphs, which can be identified efficiently, in parallel. The authors extend Eppstein's results and show in a unified manner how to solve problems on series parallel graphs efficiently, in parallel, by finding a special ear decomposition of the graph. They demonstrate the utility of their novel framework by presenting O(log n) concurrent read exclusive write (CREW) parallel random access machine (PRAM) algorithms for the construction of a depth-first spanning tree, st-numbering, and a breadth-first spanning tree on series parallel graphs. >

Parallel recognition algorithms for chordal_planar graphs and planar [formula omitted]-trees