Single-Electron Transistor Based on Cobalt Oxide

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

The present paper discusses the investigation of electronic properties of anthracene-based single electron transistor (SET) operating in coulomb blockade region using Density Functional Theory (DFT) based Atomistix toolkit-Virtual nanolab. The charging energies of anthracene molecule in isolated as well as electrostatic SET environments have been calculated for analyzing the stability of the molecule for different charge states. Study also includes the analysis of SET conductance dependence on source/drain and gate potentials in reference to the charge stability diagram. Our computed charging energies for anthracene in isolated environment are in good agreement with the experimental values and the proposed anthracene SET shows good switching properties in comparison to other acene series SETs.

Electrons in a single electron transistor (SET) are transported one by one from source to drain based on the coulomb blockade mechanism. The transport rate is sensitively influenced by the presence of event a single electron charge located near the quantum dot. Based on this characteristic, we propose a Double Quantum Dot (DQD) SET to manipulate the presence of an electron in Quantum Dot (QD) as an implementation of a single-electron logic concept. The existence of an electron in the QD is used to represent logic 0 (no electron in QD) or logic 1 (an electron in QD). The logic states are sensed by a SET charge detector. Design of circuit based on DQD and SET charge detector are simulated by using SIMON 2.0 software. From the simulation, we have successfully developed a two-bit logic circuit by controlling the presence of an electron in DQD. We found that the existence of an electron in QD can be controlled by application of a gate voltage larger than 190µV. Gate should be separated from QD by a nontunnel capacitor of 500 aF. No larger than 1 aF of interdot tunnel capacitance is required to isolate the QD from one to another. The existence of an electron in QD is successfully detected by SET based charge detector.

Single electron transistors (SETs) has been proposed as a future basis for nanoelectric components. SETs, which utilize Coulomb blockade effect arising from the electrostatic charging energy of a single electron, are one of the promising candidates for future integrated circuits due to their extremely low power consumption and high-density integration. Here, we report on the study of the formation mechanism of a nanometer-scale Au chain on a patterned SiO 2 based wafer by controlling the reaction of raw materials to form citrate Au sol and aminosilane/dithiol treated SiO 2/ Si wafer. Three gold colloidal particles (~15 nm) were aligned in a chain to form a one-dimensional current path which was bridged on a 80 nm gap between source and drain metal electrode. The SET device exhibited a Coulomb blockade effect at 40 K.

In this paper theoretical concepts based on analytical models for Single Electron Transistor (SET) are presented. It has been observed that the fabrication technology has reached on its limits for the MOS feature size, beyond which further scaling of the channel is not achievable. Due to which SET is considered as the future of the complex IC fabrication by replacing MOS technology, having small quantum dot or island, instead of channel. Working of the SET is based on the Coulomb blockade principle which is the heart of the technology. Quantum mechanics is the physics used for explaining the tunnelling of single electron of SET, which says that the energy levels are quantized not continuous. Main reason behind the advancement in SET is the market requirement of the low power, high density and fast switching devices. These are possible by SET; no doubt speed is an issue for the memories designed with SET, with its low gain and high input impedance. In the review, mathematical model including tunnelling effect in junction, coulomb blockade, current equation, free energy equation based on Shcrodinger's wave equation are presented.

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Modeling and analysis of energy quantization effects on single electron inverter performance

Single-electron transistors (SETs) are nano devices which can be used in low-power electronic systems. They operate based on coulomb blockade effect. This phenomenon controls single-electron tunneling and it switches the current in SET. On the other hand, co-tunneling process increases leakage current, so it reduces main current and reliability of SET. Due to co-tunneling phenomenon, main characteristics of fullerene SET with multiple islands are modelled in this research. Its performance is compared with silicon SET and consequently, research result reports that fullerene SET has lower leakage current and higher reliability than silicon counterpart. Based on the presented model, lower co-tunneling current is achieved by selection of fullerene as SET island material which leads to smaller value of the leakage current. Moreover, island length and the number of islands can affect on co-tunneling and then they tune the current flow in SET.

Atomic-scale probing of metallic and semiconductor nanostructures

Single-photon detection of THz waves is realized by using two kinds of detectors. The first type of detector exploits a semiconductor lateral quantum dot in magnetic fields. The quantum dot is operated as a single electron transistor (SET) to detect individual events of THz-photon absorption (1.5 THz-1.9 THz) due to cyclotron-resonance induced intra-dot polarization. The second type detector utilizes parallel double quantum dots, in which one of the quantum dots serve as an SET while the other quantum dot affects the SET conductance when it is ionized by a THz photon absorption (about 0.5 THz). The detector performance is described. A future perspective for further improvements of the detectors is also briefly given.

We investigate the possibility to implement low-energy consuming binary logic gates by means of charge sensing in electrostatically defined quantum dots (QDs) formed in single electron transistors (SETs). In the proposed logic devices, the input signals are represented by the voltage levels at the SET's gate electrodes, and the output is determined by the electrical current in the charge sensor (CS) circuit. In contrast to previous proposals of SET-based logic, the output signal does not depend on the electrical current through SET, but is defined by its charge configuration in the Coulomb blockade regime. Such a logic implementation suppresses the shot noise without increasing energy consumption.

Single electron transistor fabricated with SOI wafer

Conceptual development regarding single electron transfer phenomena is presented. It is shown that energy necessary to place a single electronic charge on one plate of a capacitor with equal opposite charge on its opposite plate is not a clearly distinguishable event at micro- and milliscales. But it becomes a meaningful event at the nanoscale due to the significant amount of energy involved. Further, it is shown that the existence of a voltage requirement for tunneling to occur across the plates of a capacitor, the so-called Coulomb blockade effect, is a noticeable phenomenon exclusive to nanoscale. Moving further, it is found that the Coulomb blockade is observable at or near room temperatures only in the scale of nano dimensions. From this understanding, the notion of a tunnel junction is put forward as a barrier in the form of an electrical potential or thin dielectric film across which tunneling occurs. The tunnel junction is modeled as an ideal capacitor with a parallel-connected tunnel resistance whose value must be ≫4.2 kΩ for Coulomb blockade to become recognizable. The capacitor of the tunnel junction behaves in a different way from a normal capacitor. Upon excitation by a constant current source , the voltage across this capacitor oscillates between two values, which are referred to as single electron tunneling oscillations . Applying the tunnel junction model, the operation of a quantum dot circuit consisting of a quantum dot and two tunnel junctions is analyzed. In both cases, for electron tunneling into the quantum dot across one tunnel junction and for electron tunneling off the quantum dot across the other tunnel junction, Coulomb blockade occurs in a quantum dot circuit like a nanocapacitor. The energy band diagram for a small quantum dot circuit exhibits a discretized nature. The electron tunneling does not take place in a continuous fashion but in discrete voltage steps. The resulting current–voltage characteristic of the quantum dot circuit has the shape of a staircase which is called the Coulomb staircase .

In this paper, the results of the study of single-electron transistor have been summarized. The advancements in fabrication technology established by the well-known Moore’s law had come to a standstill until the idea of using a single electron for operations came into effect. This single-electron transistor is a great revolution in research in nanotechnology. It uses a nanoscale island of charges called quantum dot for conductance and uses principles of ‘Coulomb Blockade’, single-electron tunneling effect. This allows miniaturization of circuits, reduced power consumption, high operating speed. These characteristics permit its application in various areas such as memory device industry, metrology. However, it has some fabrication issues which have not been fixed yet. At room temperature, a sub-nanometer island size is required for proper functioning and obtaining a good control over nanoparticle size is challenging. A comparison between SET and other conventional transistors has also been made.

Electron transport has been studied by measurement and simulation of single electron transistors based on nanocrystalline silicon (nc-Si). Nanocrystalline silicon is formed in the gas phase of the SiH4 plasma cell by the coalescence of radicals. Digital chemical vapor deposition [CVD] technique using pulsed gas in the plasma is effective to obtain highly uniform Si quantum dots with an average size of 8 nm and dispersion of 1 nm. Single electron transistors have been successfully fabricated by deposition of nc-Si on top of heavily doped silicon nanoelectrodes with a gap of 15 nm which allows the study of electron transport through two or three nanocrystals. Coulomb blockade and Coulomb oscillations are observed in these devices at various temperatures, including room temperature. The observed Coulomb diamond structure is not as simple as in the case of metallic islands. With increasing gate voltage, the spacing between oscillation peaks decreases and the Coulomb diamonds reduce in size. These observations are explained on the basis of electron transport through a quantum dot with an energy gap between the highest occupied and the lowest unoccupied electron states. Modeling of such a system can reproduce measured electrical characteristics. The unequal spacing of gate oscillations and the reduced size of Coulomb diamonds are due to the interplay of Coulomb charging energy and the energy separation between the quantized energy levels.