Single-Input Multi-Output High Conversion Ratio Hybrid Structure Buck-Boost DC-DC Converter for Energy Harvesting

Buck-boost DC–DC converters are useful as DC grid interfaces for renewable energy resources. In the classical buck-boost converter, output voltages smaller than the input voltage (the buck region) are observed for duty cycles between 0 and 0.5. Several recent buck-boost converters have been designed to present higher voltage gains. Nevertheless, those topologies show a reduced duty-cycle range, leading to output voltages in the buck region, and thus require the use of very low duty cycles to achieve the lower range of buck output voltages. In this work, we propose a new buck-boost DC-DC converter that privileges the buck region through the extension of the duty-cycle range, enabling buck operation. In fact, the converter proposed here allows output voltages below the input voltage even with duty cycles higher than 0.6. We present the analysis, design, and testing of the extended buck-boost DC-DC converter. Several tests were conducted to illustrate the characteristics of the extended buck-boost DC-DC converter. Test results were obtained using both simulation software and a laboratory prototype.

This paper is a review on 4 phase 8/6 switched reluctance motor (SRM) powered by solar PV array using the buck-boost dc-dc converter. The water pumping system is operating SRM. The main objective of this paper is to regulate the speed of SRM drive to pump the water through the DC link voltage of a mid-point converter. The split capacitor converter for SRM drive called as mid-point converter is electronically commutated to reduced switching losses. This motor is inexpensive, reliable and efficient than conventional DC and AC electrical machines used in this application, because of its simple construction. The losses in mid-point converter can be reduced by using SRM drive at its fundamental frequency and also the efficiency of the proposed system can be increased. The DC-DC buck-boost converter is working in continuous conduction mode (CCM). The CCM operation decreases the losses of DC-DC converter. The soft starting of 4 phase 8/6 SRM drive is also achieved through proper selection of step-size in incremental conductance (InC) algorithm method of maximum power point tracking (MPPT). The DC-DC buck-boost converter is the unique converter which allows excellent tracking of PV array maximum MPP rather than of temperature and insolation levels.

In recent years, active-matrix organic light-emitting diode (AMOLED) technology has been widely employed in various display applications, thanks to its higher image quality and lower power consumption. With the spread of AMOLED displays, the need for regulated negative power supplies and, hence, high-efficiency inverting buck-boost (IBB) dc-dc converters to power the pixels has arisen [1] –[3]. This paper proposes a novel IBB hybrid structure, which combines a switched-capacitor (SC) and a 3-level (3L) architecture in order to lower the inductor current and avoid exceeding its saturation limit, while maintaining high efficiency.

This paper presents a fully integrated single-inductor dual-output (SIDO) buck-boost or boost-boost DC-DC converter with power-distributive control. This converter works under voltage mode control to have better noise immunity, uses fewer power switches/external compensation components to reduce cost, and is thus suitable for system on chip (SoC) applications. The proposed SIDO converter was fabricated in TSMC 0.35μm 2P4M CMOS technology with input supply voltage 2.7–3.3 V. The first output V O1 can operates either at buck mode or boost mode (output voltage in between 2.5V to 5V), while the second output V O2 can only operates at boost mode (output voltage 3.6V).

Indoor energy harvesting using small photovoltaic (PV) cells is still not widely exploited. It can be a solution to supply ultra-low power (ULP) devices for Internet of Things (IoT) applications. However, a PV cell may suffer shading caused by walls, furniture, and human movements. This requires an efficient conversion system that can adapt to voltage variations, demanding a specific adjustable DC-DC converter. The present work aims to propose a fully integrated conversion system for indoor photovoltaic energy harvesting capable to provide a range of voltage conversion ratios (VCRs) suitable for ULP and ultra-low voltage (ULV) applications. The proposed converter is based on a reconfigurable switched-capacitor (SC) topology. A systematic simulation-based methodology for designing the DC-DC converter is presented, including switches and capacitors sizing and operating frequency optimization. Results show that the proposed circuit can obtain 19 different VCRs with an estimated peak efficiency of 94.26%. This is an important step towards a practical self-powered indoor system for IoT applications.

This paper presents a novel control method to improve the efficiency of low-voltage DC-DC converters at light loads. Pulse Width Modulation (PWM) converters have poor efficiencies at light loads, while pulse frequency modulation (PFM) control is more efficient for the same cases. Switching losses constitute a major portion of the total power loss at light loads. To decrease the switching losses and to increase efficiency, converters based on soft-switching are utilized. This paper presents the design of a soft-switching DC-DC buck converter in a 90-nm CMOS technology. Simulation results by HSPICE shows a 21 mV output ripple on a 0.5 V output voltage for an input voltage of 1.4 V. Finally, the efficiency of 95% at a load current of 50 mA having 74 mA of current ripple is achievable.

The main theme of this paper is to propose a novel switching control method for bridgeless PFC converter to improve the efficiency by reducing both switching and conduction losses. Comparing to the conventional method, the power device is always on (no switching loss) to provide a current path via the turn-on resistor of MOSFET to reduce conduction losses under light load condition. As the load increases, the power device is always off (no switching loss) to provide a current path via the body diode of MOSFET to reduce conduction losses under heavy load condition. In this paper, both simulation and experimental results will be shown to confirm the effectiveness of the proposed switching control method. Test results derived from a digital-controlled 1.2 kW PFC show the efficiency improvement can go up to 0.73% and 0.57% under full load and light load conditions, respectively. It will also be confirmed this efficiency improvement has no impact on the power factor and just simply changing the switching control method. Both measured steady state and transient waveforms will be shown for confirmation.

A comprehensive framework for the analysis and design of multiphase, reconfigurable switched-capacitor (SC) dc-dc converters is presented. A generalized method, utilizing graph theory and network analysis, is first proposed, which enumerates all attainable ideal conversion ratios for a given SC converter structure. From this analysis, the performance limits of multiphase SC converters are expanded, and a reconfigurable, multiphase SC dc-dc converter is proposed. The converter utilizes a programmable and optimized switching configuration that can generate an increased number of attainable ideal conversion ratios for the given number of capacitors and switching states. This property allows the converter to maintain high efficiency across a wide range of operating conditions and achieve very high step-up and step-down conversion ratios. A set of sample switching sequences are provided to generate any attainable ideal conversion ratio, for up to four capacitors, using a minimal number of switching states. An experimental prototype of the converter has been designed and fabricated as an integrated circuit using 0.35-μm CMOS technology to validate the performance.

A step-up/step-down DC-DC converter with high efficiency and small output voltage ripple is proposed in this paper. To reduce the switching loss and improve the efficiency, the converter operates in buck or boost mode when the input voltage is much higher or lower than the output voltage. However, a large output voltage ripple appears at the boundary of buck mode and boost mode due to the speed limitation of standard analog circuit. A transition mode using a digital dither technique is adopted and the output voltage ripple is reduced when the input voltage is close to the output voltage. Furthermore, the average inductor current is also reduced in the proposed transition mode. The converter has been designed with a standard a 0.5 μm CMOS process. The peak efficiency is 96% and the output voltage ripple is reduced to less than 10 mV in the transition mode.

To achieve wide-range power regulation without using additional dc–dc, phase-shift full-bridge (PSFB) for wireless power transfer (WPT) system is a promising way. However, for the PSFB WPT system, switching loss is a key factor affecting the system efficiency. Single-side PSFB can regulate the power, but hard switching results in low efficiency and EMI problems. Dual-side PSFB can realize ZVS throughout a wide power range, but at the cost of high conduction loss and turn-off loss at light load. In this article, a WPT converter combining tandem half bridge (THB) and active rectifier (AR) is proposed to reduce the switching loss of the system at light and medium loads. Meanwhile, an optimized hybrid triple-phase-shift (TPS) and extended-phase-shift (EPS) control strategy is proposed to achieve ZVS and power regulation with adaptive modes, thus further reducing conduction loss and switching loss and optimizing light-load efficiency. Finally, A 1.2 kW experimental prototype was built, and the experimental results indicate strong agreement with theoretical analysis. All switches realize ZVS within the entire power range and maintain high efficiency ≥94.1%) in the power range of 16.7%–100%.

In this paper, a new quasi-Y source buck-boost dc-dc converter is proposed. The proposed converter uses a quasi-Y impedance network, which consists of a three-winding transformer, or three tightly coupled inductors. The proposed converter inherits all the advantages of the original quasi-Y source dc-dc converter such as continuous input current, lack of saturation in the magnetic core of the transformer, small duty cycle and high gain. The advantage of the proposed converter is adding the buck-boost ability to the conventional structure, which is crucial for some applications such as wind turbines and battery charging systems, which demand a buck-boost converter in their structure. The mathematical analyses are provided in order to investigate the operation principles of the converter. Also, in order to verify the proper functioning of the proposed converter, simulations are done in PSCAD/EMTDC and the results and waveforms are provided in the paper.

Modern power systems face challenges due to the increasing use of renewable energy sources. To overcome these challenges, cascaded H-bridge (CHB) static synchronized compensators (StatComs) have emerged as promising solutions. CHB StatComs offer the advantage of directly regulating grid voltage and power factor at medium and high voltage levels without the need for additional low-frequency transformers. However, in order to attain the desired medium and high voltage levels, a large number of H-bridge submodules (SMs) are required. Despite each individual SM processing a relatively low voltage, it has to carry the entire leg current. This results in significant switching loss that needs to be carefully considered to ensure thermal reliability and optimal system efficiency in CHB StatComs. Discontinuous pulsewidth modulation (DPWM) is a technique that has gained research attention for its ability to reduce switching loss. In CHB StatComs with a star configuration, DPWM is achieved by injecting a zero-sequence voltage (ZSV) between the neutral of the converter and system ground, which clamps a converter leg ac-side voltage to a fraction of its corresponding cluster voltage (sum of dc-side capacitor voltages per converter leg). The clamped converter leg stops switching, resulting in reduced switching loss. However, unlike two-level converters where a common dc-link is shared by three phases, the single-phase configuration of CHB StatComs, along with the use of floating capacitors in the dc-side of each SM, complicates the use of conventional DPWM methods. This complication is further exacerbated during grid imbalances, as the interaction between grid currents and the ZSV for DPWM can result in nonzero active power transfer to each leg, leading to divergence in cluster voltages and causing performance degradation. To solve this problem, the thesis focuses on developing advanced DPWM techniques that ensure effective cluster voltage control, even under severe grid imbalances, while simultaneously optimizing other control objectives, such as minimizing switching loss. The thesis first identifies a suitable DPWM method for CHB StatComs and analyzes its advantages in terms of capacitance reduction, switching loss reduction, enlargement of the inductive operation range, and reduction of converter voltage total harmonic distortion. The DPWM is then enhanced by considering the possibility of clamping to the zero-voltage level, providing benefits such as lower ZSV magnitude requirements and further reduction in switching loss. Subsequently, the thesis formulates DPWM as a finite-set optimization problem, proposing different cost functions to optimize the control objectives. This finite-set optimization formulation enables the embedding of cluster voltage control into DPWM implementation using model predictive control approaches, significantly enhancing the dynamical performance of CHB StatCom. The thesis evaluates the impact of the proposed DPWM methods on capacitor lifetime, highlighting the tradeoff between switching loss minimization and capacitor lifetime maximization. Finally, the thesis suggests future research directions, such as exploring increased clamping possibilities by considering the option of clamping to intermediate voltage levels. This novel concept has the potential to optimally address the aforementioned tradeoff between capacitor lifetime and converter switching loss. The thesis offers significant contributions to the field by effectively decoupling DPWM implementation from CHB StatCom cluster voltage control, making DPWM a feasible and reliable solution for next-generation CHB StatCom applications. Additionally, it introduces advanced DPWM strategies that allows the optimization of dedicated control objectives. Case studies demonstrate significant improvements when different control objectives are prioritized, such as a reduction of more than 45% in switching loss, an increase of over 10% in capacitor lifetime, an expansion of more than 50% in the inductive operation range, and a decrease of over 20% in dc capacitor capacitance compared to conventional sinusoidal pulsewidth modulation. The study of the thesis represents a crucial step towards fully leveraging the potential benefits of intelligently utilizing ZSV in CHB StatComs, thereby advancing CHB StatComs with improved reliability and efficiency performance. The findings presented in this thesis can benefit the design and operation of CHB StatComs, as well as other power system applications.

The buck-boost DC-AC inverter generates an alternating output voltage as the differential voltage of two DC-DC individual buck-boost converters that are driven with two 180/spl deg/ phase-shifted DC-biased sinusoidal references. The peak value of the inverter alternating output voltage does not depend on the direct input voltage. In addition, an advantage over the Boost DC-AC inverter is that the output voltages of both Buck-Boost converters are also independent of the direct input voltage. The difficulty of the topology lies in the control of both buck-boost DC-DC converters as they are required to work with variable operating-points. A double-loop control strategy is proposed for the buck-boost DC-DC converter with a new inner control loop for the inductor current and also a new outer control loop for the output voltage. These control schemes include different compensations that make possible a fast and accurate control of both converters with variable operating points. With these compensations, the controllers are easy to design, implement and develop. Furthermore, feedforward loops are included to increase the robustness of the inverter to external disturbances in both the input voltage and output load. The proposed control strategy is designed and implemented on a prototype 1.5 kW buck-boost DC-AC inverter. The control strategy is validated by means of both simulation and experimental tests. The results show that the proposed strategy achieves a robust, reliable and accurate control of the inverter even in hard situations such as nonlinear loads, sudden load changes and transient short circuits.

This paper presents a novel method for making Capacitive De-Ionizatrion (CDI) water purification more efficient and cheaper, using a buck-boost DC-DC converter. The energy recovery is superior (51%) versus maximum reported results in the literature (30%) [1]. First, the concept of a CDI cell is introduced. Second, the existing methods for energy recovery are reported showing their advantages and disadvantages. Then, the novel method using a buck-boost converter is presented. Simulation results are provided. Experimental data verified the new technique and agrees with simulation.

A multi-mode control strategy (MMCS) is proposed to improve the efficiency of three-level (3L) DC-DC converter under light-load and standby conditions without auxiliary components. 3L converter is typically controlled in phase-shift control mode (PSCM) in order to achieve zero-voltage-switching (ZVS) to reduce switching loss with rated load. However, since little energy is provided to discharge the parasitic capacitors of the switches, light load leads to hard switching and makes efficiency drop in PSCM. The proposed control strategy aims to overcome this problem. It consists of three modes: PSCM to reduce switching loss with heavy load, pulse-width-modulated control mode (PWMCM) to reduce conduction loss with light load and PWM burst control mode (PWMBCM) to further reduce unnecessary loss under standby condition. A 120V, 1.5kW prototype has been made to validate this control strategy. The efficiency of the 3L converter is increased by up to 24.7 percentage points under standby condition and 3.7 percentage points with light load.