Single-Shuffle Card-Based Protocol with Eight Cards per Gate

Card-based cryptography allows us to securely compute arbitrary functions using a deck of physical cards. Its performance is mainly measured by the number of used cards and shuffles, and there is a line of work that aims to reduce either of them. One seminal work is the card-based garbled circuit technique by Shinagawa and Nuida (Discret Appl Math 289:248–261, 2021, https://doi.org/10.1016/j.dam.2020.10.013), which allows the construction of a card-based protocol for any Boolean function with a single shuffle. Their construction requires 2n+24g cards for an n-input Boolean function that is represented by g logical gates. In this paper, we reduce the number of cards to 2n+8g for arbitrary functions while keeping it working with only one shuffle. In addition, we propose two types of extensions to support numerical encoding and multi-input gates. In the extended scheme, the free-ADD technique, obtained by generalizing the free-XOR technique by Manabe and Shinagawa (Deng J, Kolesnikov V, Schwarzmann AA (eds) CANS 2023, LNCS, vol 14342. Springer, Singapore, pp 232–248, 2023, https://doi.org/10.1007/978-981-99-7563-1-11), is available. The free-ADD technique allows our scheme to evaluate any n-input symmetric Boolean function using 2n2+6n+2 cards.

It is established that secure computation can be achieved by using a deck of physical cards. Almost all existing card-based protocols are based on a specific deck of cards. In this study, we design card-based protocols that are executable using any deck of cards (e.g., playing cards, UNO, and trading cards). Specifically, we construct a card-based protocol for any Boolean function based on any deck of cards. As corollaries of our result, a standard deck of playing cards (having 52 cards) enables secure computation of any 22-variable Boolean function, and UNO (having 112 cards) enables secure computation of any 53-variable Boolean function.

Robust template design for cellular neural networks (CNNs) implementing an arbitrary Boolean function is currently an active research area. If the given Boolean function is linearly separable, a single robust uncoupled CNN can be designed preferably as a maximal margin classifier to implement the Boolean function. On the other hand, if the linearly separable Boolean function has a small geometric margin or the Boolean function is not linearly separable, a popular approach is to find a sequence of robust uncoupled CNNs implementing the given Boolean function. In the past research works using this approach, the control template parameters and thresholds are usually restricted to assume only a given finite set of integers. In this study, we try to remove this unnecessary restriction. NXOR- or XOR-based decomposition algorithm utilizing the soft margin and maximal margin support vector classifiers is proposed to design a sequence of robust templates implementing an arbitrary Boolean function. Several illustrative examples are simulated to demonstrate the efficiency of the proposed method by comparing our results with those produced by other decomposition methods with restricted weights.

The concept of truth table is based on the content to analyze in teaching and learning logical reasoning and logic gate, which is a visual representation of possible combination of input and output information of Boolean prepositions in logical reasoning and Boolean functions in logic gate plotted into a table. It adopts Boolean algebra for problem solving as a method or science of reasoning, or ability to argue and convince. In the teaching and learning processes of logic, formal and informal reasoning tasks are used in a variety of ways, including using symbols and entirely in plain language without symbols where symbolic logics are commonly referred to as mathematical logic. This paper therefore considers the Use of Truth Table, Logical Reasoning and Logic Gate in Teaching and Learning Process It highlighted the benefits of using the truth table and compared logical reasoning and logic gate connectives and concluded that, there exist similarities, differences and peculiarities in the interactive features of the content of the truth table. The paper suggested that teachers should vividly state the similarities, differences and peculiarities in the interactive features of truth table in logical reasoning and logic gate while incorporating thought in teaching and learning process to avoid confusion.

Abstract. Background. Computer circuits enable almost every piece of electronics to function. An opportunity for their optimization was found in one of the ways to implement a circuit, which involves a decoder. Decoders are basic circuit components whose behavior makes it easy to implement multiple Boolean functions. Functions are just rules by which informational signals are being processed in the circuit. To implement a function Logic gatEs (LEs) are used. LEs group multiple input signals and process them using binary logic operators like AND or NOR. Purpose. Develop a computer program that, based on provided functions, will find a solution associated with approximately minimal number of logic gates. Relevance. Prevalence of circuits increases the value of small optimizations, since any improvement gets multiplied by millions of circuits produced. Optimization at the logic level is being explored, which will retain value regardless of the physical properties of the circuit. Additionally, the theory of optimizing LE usage for circuits built on decoders is examined, which will alleviate future research. Methods. Development of the theory arose from an understanding that input signals can be grouped using LEs consciously. This way, LE outputs can be used in more than one function, which results in reduction of total number of LEs. It becomes evident that the problem can be restated in terms of sets. Similarity to known NP-hard problems emerges, which prompts usage of existing solution approaches. Among them, the greedy algorithm is chosen for its simplicity in program implementation. The connection between the problem and digital circuitry is weakened by the introduction of special evaluation functions that work with sets. So, the problem is reduced to several mathematical rules, which then are used as the appropriate parts of the greedy algorithm. Development of knowledge necessary to create the target program is thus concluded. Results. The target program is successfully implemented and can be seen in full at https://github.com/Gleb-05/MakeFuncForDC. A test is conducted on 1000 sets of four pseudorandom eight-term functions. It is estimated that the implementations proposed by the program require on average 0.75 of the initial number of LEs. The average running time is estimated at 2 milliseconds. In contrast, brute-force search for the same problem is theorized to run for years. Conclusions. A working program that finds an almost optimal solution is successfully created and tested. Its performance makes it potentially useful in the industrial scale of circuit manufacturing. Since the program essentially offers workload management, its possible applications go beyond the domain of digital electronics. Additionally, the theory of optimizing the use of LEs is presented for the first time. It can be used as the basis for future research on the implementation of multiple Boolean functions using decoder.

A Boolean function $f:A_1 \times A_2 \times \cdots \times A_n \to \{ 0,1 \}$ is t-private if there exists a protocol for computing f so that no coalition of size $\leqq t$ can infer any additional information from the execution, other than the value of the function. It is shown that f is $\lceil n/2 \rceil $-private if and only if it can be represented as \[ f ( x_1 ,x_2 , \cdots ,x_n ) = f_1 ( x_1 ) \oplus f_2 ( x_2 ) \oplus \cdots \oplus f_n ( x_n ), \] where the $f_i $ are arbitrary Boolean functions. It follows that if f is $\lceil n/2 \rceil $-private, then it is also n-private. Combining this with a result of Ben-Or, Goldwasser, and Wigderson, and of Chaum, Crepeau, and Damgard, [Proc. 20th Symposium on Theory of Computing, 1988, pp. 1–10 and pp. 11–19] an interesting “zero-one” law for private distributed computation of Boolean functions is derived: every Boolean function defined over a finite domain is either n-private, or it is $\lfloor ( n - 1 )/2 \rfloor $-private but not $\lceil n/2 \rceil $-private. A weaker notion of privacy is also investigated, where (a) coalitions are allowed to infer a limited amount of additional information, and (b) there is a probability of error in the final output of the protocol. It is shown that the same characterization of $\lceil n/2 \rceil $-private Boolean functions holds, even under these weaker requirements.In particular, this implies that for Boolean functions, the strong and the weak notions of privacy are equivalent.

We study the complexity of the realization of Boolean functions by circuits in infinite complete bases containing all monotone functions with zero weight (cost of use) and finitely many nonmonotone functions with unit weight. The complexity of the realization of Boolean functions in the case where the only nonmonotone element of the basis is negation was completely described by A. A. Markov: the minimum number of negations sufficient for the realization of an arbitrary Boolean function f (the inversion complexity of the function f) is equal to ⌈log2(d(f) + 1)⌉, where d(f) is the maximum (over all increasing chains of sets of values of the variables) number of changes of the function value from 1 to 0. In the present paper, this result is generalized to the case of the computation of Boolean functions over an arbitrary basis B of prescribed form. It is shown that the minimum number of nonmonotone functions sufficient for computing an arbitrary Boolean function f is equal to ⌈log2(d(f)/D(B) +1)⌉, where D(B) = max d(ω); the maximum is taken over all nonmonotone functions ω of the basis B.

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.

If the given Boolean function is linearly separable, a robust uncoupled cellular neural network can be designed as a maximal margin classifier. On the other hand, if the given Boolean function is linearly separable but has a small geometric margin or it is not linearly separable, a popular approach is to find a sequence of robust uncoupled cellular neural networks implementing the given Boolean function. In the past research works using this approach, the control template parameters and thresholds are restricted to assume only a given finite set of integers, and this is certainly unnecessary for the template design. In this study, we try to remove this restriction. Minterm- and maxterm-based decomposition algorithms utilizing the soft margin and maximal margin support vector classifiers are proposed to design a sequence of robust templates implementing an arbitrary Boolean function. Several illustrative examples are simulated to demonstrate the efficiency of the proposed method by comparing our results with those produced by other decomposition methods with restricted weights.

Reductions for monotone Boolean circuits

MOS networks and fault-tolerant sequential machines

One of the main security criteria that mostly influence the strength of a conventional cipher system is the Nonlinearity criterion. A classical cipher system is considered strong if it is characterized by high nonlinearity. That is, the underlying Boolean function employed within the system is required to be far from being linear. The measure of a Boolean function's nonlinearity can be done with the help of the Walsh transform as a tool. This paper presents an analysis of the nonlinearity criterion from the Haar transform domain perspective. The paper proceeds by utilizing the connection between the Haar and the Walsh transforms. The work provides two main contributions in the form of the definition of nonlinearity given the Haar spectrum of an arbitrary Boolean function and a Haar-Walsh hybrid algorithm for measuring the nonlinearity given the Haar spectrum. The derived algorithm is then simulated along with the Walsh benchmark and the results are presented in a comparison study. The paper then follows up by presenting a discussion on the computational advantages of employing the Haar-Walsh hybrid method in terms of time and space complexities. It is shown that, the Haar-Walsh hybrid method performs better when the transformed function is characterized by high number of input variables (n > 11). The paper concludes with a summary of the presented work and suggestions for future work.

A decomposition and reconstruction approach for synthesizing an arbitrary Boolean function with a minimum number of threshold logic elements connected by feedforward paths only is presented. Attention is mainly focused on cascade-type realizations. The approach has the advantage that near-minimal solutions are readily derived. An estimate of how closely the minimality has been approached is obtainable in this method. The method has been successfully applied by the authors to Boolean functions of 5 and 6 variables.

The class of affine Boolean functions is rich enough to express constant bits and dependencies between different bits of different words. For example, the function (x0) ∧ (¬y1) ∧ (x4 ⇔ y7) ∧ (x5 ⇔ ¬y9) is affine and expresses the invariant that the low bit (bit 0) of the variable x is true, that bit 1 of y is false, that the bits 4 and 7 of x and y coincide whereas bits 5 and 9 of x and y differ. This class of Boolean function is amenable to bit-precise reasoning since it satisfies strong chain properties which bound the number of times a system of semantic fixpoint equations need to be reapplied when reasoning about loops. This paper address the key problem of abstracting an arbitrary Boolean function to either a general affine function or a so-called affine function of width 2, when the function is represented as an ROBDD. Novel algorithms are presented for this task: one that manipulates Boolean vectors and another which is inspired by anti-unification. The speed and precision of both algorithms are compared on benchmark circuits, to draw conclusions on the tractability of affine abstraction.

100 Gb/s all-optical multifunctional AND, NOR, XOR, OR, XNOR, and NAND logic gates in a single compact scheme based on semiconductor optical amplifiers