Small moduli replications in the MRRNS

A modular architecture for very fast digital signal processing (DSP) elements are presented. The computation is performed over finite rings (or fields) and is able to emulate processing over the integer ring using residue number systems. The computations are restricted to closed operations (ring or field binary operators) with the ability to perform limited scaling operations. Computations naturally defined over finite mathematical systems are also easily implemented using this approach. The technique evolves from the decomposition of each closed calculation using the ring/field associativity property. Linear systolic arrays, formed with multiple elements, each of a single generic form, are used for all calculations. The pipeline cycle is determined from the generic cell and is predicted to be very fast by a critical path analysis. The cells are matched to the VLSI medium, and the resulting array structures are very dense. Examples of DSP applications are given to illustrate the technique, and example cell and array VLSI layouts are presented for a 3- mu m CMOS process. >

The first order logic \(\mathcal{R}ing(0,+,*,<)\) for finite residue class rings with order is presented, and extensions of this logic with generalized quantifiers are given. It is shown that this logic and its extensions capture DLOGTIME-uniform circuit complexity classes ranging from AC 0 to TC 0. Separability results are obtained for the hierarchy of these logics when order is not present, and for \(\mathcal{R}ing(0,+,*,<)\) from the unordered version. These separations are obtained using tools from class field theory, adapting notions as the spectra of polynomials over finite fields to sets of sentences in this logic of finite rings, and studying asymptotic measures of these sets such as their relative densities. This framework of finite rings with order provides new algebraic tools and a novel perspective for descriptive complexity.

Separations among the first order logic Ring(0,+, ∗) of finite residue class rings, its extensions with generalized quantifiers, and in the presence of a built-in order are shown, using algebraic methods from class field theory. These methods include classification of spectra of sentences over finite residue classes as systems of congruences, and the study of their h-densities over the set of all prime numbers, for various functions h on the natural numbers. Over ordered structures the logic of finite residue class rings and extensions are known to capture DLOGTIMEuniform circuit complexity classes ranging from AC to TC. Separating these circuit complexity classes is directly related to classifying the h-density of spectra of sentences in the corresponding logics of finite residue classes. We further give general conditions under which a logic over the finite residue class rings has a sentence whose spectrum has no h-density. One application of this result is that Supported by MICINN project TIN2011-27479-C04-03 (BASMATI), MINECO project TIN201457226-P (APCOM) and Gen. Cat. project SGR2014-890 (MACDA).

Sense and sensibility: of synthetic biology and the redesign of bioreporter circuits.

Several works have been conducted regarding the reduction of the energy consumption in electrical circuits. Reversible circuit synthesis is considered to be one of the major efforts at reducing the amount of power consumption. The field of reversible circuit synthesis uses a large number of proposed algorithms to minimize the overall cost of circuits synthesis (represented in the line number and quantum cost), with minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter which needs to be tackled, especially for large-scale circuits which need to be realized by cascades of reversible gates. Reducing the synthesis cost can be achieved by Binary Decision Diagrams (BDDs), which are considered to be a step forward in this field. Nevertheless, the mapping of each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we implement the idea of the subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuit synthesis time. Considering Depth-First Search (DFS), we convert an entire BDD subtree in one step into a cascade of reversible gates. A look-up table for all possible combinations of subtrees and their corresponding reversible gates has been constructed, in which a hash key is used to directly access subtrees during the mapping process. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95% on average), preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.

A numerical procedure is presented for the scaling of lean aeronautical gas turbine combustors to different thrust classes. The procedure considers multiple operating points and aims for a self-similar flow field with respect to a reference configuration. The developed scaling approach relies on an optimization-based workflow which involves automated geometry and numerical grid generation, unsteady Reynolds-averaged Navier–Stokes (URANS) simulations, and postprocessing of the reacting flow field. Kriging is applied as a metamodel to identify new sets of parameters for combustor geometry generation. A generic lean-burn high-pressure aeronautical combustor has been designed to serve as a first verification test case with reactive flow characteristics comparable to real combustion chambers. The burner geometry is parameterized by 23 free parameters which are altered within the scaling process. The definition of a suitable scaling function is essential for the success of the scaling approach. A scaling function based on pressure loss, axial location of heat release, pilot air split, and the temperature profile at the combustor exit is proposed. The developed procedure is tested and applied for the scaling of an internally-staged lean combustor to a lower thrust class considering multiple operating points simultaneously. In total, 65 different combustor variants have been evaluated by the scaling procedure. Simulations were performed for each of these configurations at takeoff, approach, and idle operating conditions. The final combustor configuration, scaled to a lower thrust class, shows good agreement to the reference configuration in terms of the scaling targets and reasonably resembles the emission indices. Integrating the scaling procedure into the design process of future combustion systems could reduce the required design iterations and thereby contribute to significantly reduced development times and costs.

We advance a scaling procedure for molecular dynamics (MD) simulations which allows for the computation of extreme ionization levels, multielectron dynamics, and Coulomb explosion (CE) energetics of very large elemental and molecular clusters driven by ultraintense (peak intensities ${I}_{M}={10}^{15}--{10}^{21}\phantom{\rule{0.3em}{0ex}}\mathrm{W}\phantom{\rule{0.2em}{0ex}}{\mathrm{cm}}^{\ensuremath{-}2}$) laser fields. The procedure of scaled particle dynamics uses a standard MD code for a scaled cluster with a reduced number of composite ions (nuclei) (heavy pseudoparticles) and of composite electrons (light pseudoparticles). A single scaling parameter $s$ was used for the composition, charge, and mass of all the pseudoparticles, while the initial distances between pseudoparticles and the short-range potential parameters were scaled by ${s}^{1∕3}$. The scaling procedure was applied for the computation of the ion energies from CE of ${({\mathrm{D}}_{2})}_{n∕2}$ and ${(\mathrm{C}{\mathrm{H}}_{4})}_{n}$ clusters over the size domain of $n={10}^{3}--{10}^{7}$, bridging between clusters and nanodroplets. Deuterons with a maximal energy of $110\phantom{\rule{0.3em}{0ex}}\mathrm{keV}$ can be effectively produced and utilized for nuclear fusion driven by CE of ${(\mathrm{D})}_{n}$ clusters with $n=1.7\ifmmode\times\else\texttimes\fi{}{10}^{6}$. The intensity dependence of the ionization levels of ${(\mathrm{C}{\mathrm{H}}_{4})}_{n}$ clusters $(n=8\ifmmode\times\else\texttimes\fi{}{10}^{4}--{10}^{6})$ manifests ignition and nanoplasma screening effects, establishing the conditions for the production of bare ${\mathrm{C}}^{6+}+{\mathrm{H}}^{+}$ nuclear matter for nucleosynthesis. The scaling procedure will be applicable for large finite systems where the particle motion is mainly governed by long-range (e.g., Coulomb) interactions.

Purpose – The purpose of this paper is to investigate strategies for expedited dimension scaling of electromagnetic (EM)-simulated microwave and antenna structures, exploiting the concept of variable-fidelity inverse surrogate modeling. Design/methodology/approach – A fast inverse surrogate modeling technique is described for dimension scaling of microwave and antenna structures. The model is established using reference designs obtained for cheap underlying low-fidelity model and corrected to allow structure scaling at high accuracy level. Numerical and experimental case studies are provided demonstrating feasibility of the proposed approach. Findings – It is possible, by appropriate combination of surrogate modeling techniques, to establish an inverse model for explicit determination of geometry dimensions of the structure at hand so as to re-design it for various operating frequencies. The scaling process can be concluded at a low computational cost corresponding to just a few evaluations of the high-fidelity computational model of the structure. Research limitations/implications – The present study is a step toward development of procedures for rapid dimension scaling of microwave and antenna structures at high-fidelity EM-simulation accuracy. Originality/value – The proposed modeling framework proved useful for fast geometry scaling of microwave and antenna structures, which is very laborious when using conventional methods. To the authors’ knowledge, this is one of the first attempts to surrogate-assisted dimension scaling of microwave components at the EM-simulation level.

15 - Magnetism of Chains and Rings

In this paper, we investigate residue number system (RNS) to decimal conversion for a three moduli set with a common factor. We propose a new RNS to binary converter for the moduli set {2n + 2, 2n + 1, 2n} for any even integer n > 0. First, we demonstrate that for such a moduli set, the computation of the multiplicative inverses can be eliminated. Secondly, we simplify the Chinese Remainder Theorem (CRT) to obtain a reverse conveter that uses mod-n instead of mod-(2n+2)(2n) or mod-2n required by other state of the art equivalent converters. Next, we present a low complexity implementation that does not require explicit use of the modulo operation in the conversion process as it is normally the case in the traditional CRT and other state of the art equivalent converters. In terms of area, our proposal requires four 2:1 adders and 2 multipliers while the best state of the art equivalent converter requires one 3:1 adder, two 2:1 adders, and four multipliers. In terms of critical path delay, our scheme requires 3 additions and 1 multiplication with mod-n operations whereas the best state of the art equivalent converter requires 2 additions and 2 multiplications with mod-2n operations. Consequently, our scheme outperforms state of the art converters in terms of area and delay. Moreover, due to the fact that our scheme operates on smaller magnitude operands, it requires less complex adders and multipliers, which potentially results in even faster and smaller implementations.

Computation over finite rings using networks modeled after the general neural network approach is discussed. In this case, the neurons are arithmetic elements that have modulo operator characteristics, rather than the usual nonlinear, saturating characteristics of learning and associative memory neural network applications. Following an analysis of finite-ring arithmetic, a computing model based on an iterative, bit-level modulo reduction scheme is built, from which a basic operator is extracted. A corresponding subnet is designed to implement this operator, and its effectiveness is illustrated in two examples of computing finite-ring operations for residual number system computations. >

In large scale data storage systems, RAID-6 has received more attention due to its capability to tolerate concurrent failures of any two disks, providing a higher level of reliability. However, a challenging issue is its scalability, or how to efficiently expand the disks. The main reason causing this problem is the typical fault tolerant scheme of most RAID-6 systems known as Maximum Distance Separable (MDS) codes, which offer data protection against disk failures with optimal storage efficiency but they are difficult to scale. To address this issue, we propose a novel Stripe-based Data Migration (SDM) scheme for large scale storage systems based on RAID-6 to achieve higher scalability. SDM is a stripe-level scheme, and the basic idea of SDM is optimizing data movements according to the future parity layout, which minimizes the overhead of data migration and parity modification. SDM scheme also provides uniform data distribution, fast data addressing and migration. We have conducted extensive mathematical analysis of applying SDM to various popular RAID-6 coding methods such as RDP, P-Code, H-Code, HDP, X-Code, and EVENODD. The results show that, compared to existing scaling approaches, SDM decreases more than 72.7% migration I/O operations and saves the migration time by up to 96.9%, which speeds up the scaling process by a factor of up to 32.

We present an optimized variant of the Brakerski/Fan-Vercauteren (BFV) homomorphic encryption scheme and its efficient implementation in PALISADE. Our algorithmic improvements focus on optimizing decryption and homomorphic multiplication in the Residue Number System (RNS), using the Chinese Remainder Theorem (CRT) to represent and manipulate the large coefficients in the ciphertext polynomials. These improvements are based on our original general-purpose techniques for CRT basis extension and scaling that can be applied to many other lattice-based cryptographic primitives. Our variant is simpler and significantly more efficient than the RNS variant proposed by Bajard et al. both in terms of noise growth and the computational complexity of the underlying CRT basis extension and scaling procedures.

The article is devoted to identifying the specific features of share conversion and substantiating the legal consequences arising from such conversion in the course of the reorganization of a joint-stock company from which a demerger is carried out. Three possible variants of the share conversion procedure in the reorganization of a joint-stock company through demerger have been identified: conversion of the shares of the joint-stock company–issuer from which the demerger is carried out into shares of the newly established companies without changing the issuer’s authorized capital; conversion of the shares of the joint-stock company–issuer from which the demerger is carried out into shares of the newly established companies with a change in the issuer’s authorized capital; conversion of the shares of the joint-stock company–issuer from which the demerger is carried out into shares of the same joint-stock company. The procedure for share conversion for each of the three demerger-related procedures has been formalized by determining a logical sequence of actions as legal facts that constitute the elements of the legal composition of the share conversion process. The legal consequences of the share conversion procedure have been established, namely: the formation of the required amount of authorized capital of the newly established successor companies through the deposit of their global certificates by the Central Securities Depository; confirmation of the legality of the conversion and admission of the shares of the newly established successor companies to the securities market through the registration by the National Securities and Stock Market Commission of reports on the results of the placement of the share issues of such companies and the issuance of share issue registration certificates; confirmation of the economic legal capacity of the newly established successor companies through their registration by state registration authorities, including the registration of their authorized capital; acquisition of ownership rights to shares and rights arising from shares (corporate rights) by the shareholders of the newly established successor companies through the transfer by the Central Securities Depository of shares from the securities accounts of the newly established issuers to the securities accounts of depository institutions where the shares of such shareholders are recorded.

Edge devices often connect to the cloud these days so they can use its storage and processing power. This brings up concerns about the safety and privacy of user data. Homomorphic encryption (HE) is a good way to protect data privacy because it lets you do any kind of elegant computation on encrypted data without ever needing to decrypt it. There have been a lot of attempts to make HE computations in the cloud faster, but less attention has been paid to the methods of converting messages to ciphertext and ciphertext to messages on the edge. This work profiles the edge-side conversion procedures, and our analysis shows that the encryption, decryption, and error sampling activities are the main problems that slow down the conversion process. To get around these problems, we present RISE, a RISCV SoC that uses less space and energy. RISE uses a lightweight and effective pseudorandom number generator core along with fast sampling methods to speed up the error sampling processes. The number theoretic transform operation is the main bottleneck in the encryption and decryption processes. RISE speeds up these processes by using scalable, data-level parallelism. Also, RISE uses strategies like memory reuse and data reordering to use as little on-chip memory as possible. It also saves space by using a single en/decryption datapath. We use a full RTL design with a RISC-V processor that is connected to our accelerator to test RISE. Our research shows that using RISE instead of just the RISC-V processor makes converting messages to ciphertext and ciphertext to messages much more energy-efficient, by up to 6191.19× and 2481.44×, respectively