SoC synthesis with automatic hardware-software interface generation

In this paper we propose an approach for automatically building real-time emulations of large scale cyber-physical energy systems. An end-to-end methodology is presented, starting from the system description, continuing with automatic model and interface generation, and finally completing with deployment and real-time execution. The intended target use of the proposed solution is the validation of massively distributed smart-grid software applications. The goal is to provide an automated testing framework that can be integrated in modern software development tool-chains. In this manner, complex software ecosystems that act on critical infrastructure can be exhaustively evaluated and validated before being deployed in the field. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A prototypical implementation is also presented. This relies on a commercially available real-time simulator whose digital interfacing capabilities were extended in order to meet our automation requirements. As a showcase we consider the problem of generator dispatch using a distributed optimal power flow algorithm. For this example application we consider two test scenarios: one consisting of a smaller network where 13 software agents are deployed, and a larger one involving 123 software agents. Using the proposed framework, scaling the test setup is automated, considerably reducing the required time and errors that typically appear during this process.

BackgroundNew diagnosis tests are urgently needed to address the global tuberculosis (TB) burden and to improve control programs especially in resource-limited settings. An effective in vitro diagnostic of TB based on serological methods would be regarded as an attractive progress because immunoassays are simple, rapid, inexpensive, and may offer the possibility to detect cases missed by standard sputum smear microscopy. However, currently available serology tests for TB are highly variable in sensitivity and specificity. Lipolytic enzymes have recently emerged as key factors in lipid metabolization during dormancy and/or exit of the non-replicating growth phase, a prerequisite step of TB reactivation. The focus of this study was to analyze and compare the potential of four Mycobacterium tuberculosis lipolytic enzymes (LipY, Rv0183, Rv1984c and Rv3452) as new markers in the serodiagnosis of active TB.MethodsRecombinant proteins were produced and used in optimized ELISA aimed to detect IgG and IgM serum antibodies against the four lipolytic enzymes. The capacity of the assays to identify infection was evaluated in patients with either active TB or latent TB and compared with two distinct control groups consisting of BCG-vaccinated blood donors and hospitalized non-TB individuals.ResultsA robust humoral response was detected in patients with active TB whereas antibodies against lipolytic enzymes were infrequently detected in either uninfected groups or in subjects with latent infection. High specifity levels, ranging from 93.9% to 97.5%, were obtained for all four antigens with sensitivity values ranging from 73.4% to 90.5%, with Rv3452 displaying the highest performances. Patients with active TB usually exhibited strong IgG responses but poor IgM responses.ConclusionThese results clearly indicate that the lipolytic enzymes tested are strongly immunogenic allowing to distinguish active from latent TB infections. They appear as potent biomarkers providing high sensitivity and specificity levels for the immunodiagnosis of active TB.

AbstractÐA methodology for the design and development of data parallel applications and components is presented. Data-parallelism is a well-understood form of parallel computation, yet developing simple applications can involve substantial efforts to express the problem in low-level notations. We describe a process of software development for data-parallel applications starting from high-level specifications, generating repeated refinements of designs to match different architectural models and performance constraints, enabling a development activity with cost-benefit analysis. Primary issues are algorithm choice, correctness, and efficiency, followed by data decomposition, load balancing, and message-passing coordination. Development of a data-parallel multitarget tracking application is used as a case study, showing the progression from high to low-level refinements. We conclude by describing tool support for the process.

In this paper, we present a model-based expert system for automatic digital systems design. The goal of digital systems design is to generate a workable and efficient design from high level specifications. The formalization of the design process is a necessity for building an efficient automatic CAD system. Our approach combines model-based, heuristic best-first search, and meta-planning techniques from AI to facilitate the design process. The design process is decomposed into three subprocesses. First, the high-level behavioral specifications are translated into sequences of primitive behavioral operations. Next, primitive operations are grouped to form intermediate-level behavioral functions. Finally, structural function modules are selected to implement these functions. Using model-based reasoning on the primitive behavioral operations level extends the solution space considered in design and provides more opportunity for minimization. Heuristic best-first search and meta-planning tech-niques control the decision-making in the latter two subprocesses to optimize the final design. They also facilitate system maintenance by separating design strategy from design knowledge.

In this paper, we will focus exclusively in the obtention of optimum power designs, using the (gm/ID) methodology. The introduction of a simple, gain bandwidth driven, automatic design algorithm for OTA is used as a starting point for the review of more advanced design methodology. This review leads to an automatic synthesis algorithm developed in MATLAB which systematically transits from high level specifications (total settling time) to the amplifier specifications (gain-bandwidth, slew rate) and then to transistor sizing. The design obtained complies with the high level specifications with minimum power consumption. Two main lines of study are followed here. The study of architectures for input and output stages that are suitable to be used on different environmental conditions, allow us to obtain an opamp cell that can be used in an ample spectrum of low-voltage, micropower applications. The second line of study in analog design reuse focuses on the possibility of circuit performance tuning through the bias current, where preliminary results have already been obtained . The idea in this technique is to tune the power-speed trade off of the opamp cell using the bias current while keeping the performance in all other aspects.

Older adults benefit from information and communication technology solutions and services in the Ambient Assisted Living (AAL) domain. Unfortunately offered user interfaces for these ICT solutions often do not take the special needs, preferences and the physical and mental capabilities of older adults into account. The project AALuis focuses on solutions to increase accessibility, adaptability and usability of user interfaces in the AAL domain. The general idea is to build a layer which can be used for different platforms to connect different types of user interfaces on different I/O devices with various AAL services. The layer shall take the burden from the service developers to design a target group friendly user interface by providing mechanisms for an automatic user interface generation. First results have shown that the chosen approach is very powerful, but as well that the automatic user interface generation process needs optimization and additional semantic information to be able to build richer user interfaces.

We present a hardware-software cosimulation environment for heterogeneous systems. To be an efficient system verification environment for the rapid prototyping of heterogeneous systems, the environment provides following features: interface transparency, smooth transition to cosynthesis, simulation acceleration, and integrated user interface and internal representation. Among them, the first two are more important than the others. To support these two features, we have developed automatic interface generation schemes. As demonstrating experiments, two heterogeneous systems performing same function with different target architectures were cosimulated and prototyped successfully in our environment. The experimental results show that our environment can be a useful heterogeneous system specification/verification environment for rapid prototyping.

Basically, aircraft engines can be divided into a control embedded system and a controlled system with its environment. The behaviour of the controlled system is given a priori, while the control system still needs to be designed in a way guaranteeing the correct overall behaviour under all operational conditions depending on the flight domain. A large quantity of functions in control systems can be described by a formal system expressed in block diagrams and state-based representations. These representations can be translated to formal based tools relying on the synchronous languages Signal and Statecharts. SACRES is a tool set supporting the design of safety-critical embedded control systems. It integrates the tools and specification techniques Statemate, Sildex, and Timing Diagrams with tool components for automatic code generation, formal verification based on model checking techniques, and an innovative approach for automatic code validation for target code generated from DC+. Technical achievements are The main benefits of the SACRES approach are reduced risks for design errors and decreased design times and costs for the development of dependable (safety critical) embedded systems. SACRES is an attempt to avoid unpredictability (particularly that arising from late feedback from testing) associated with development of safety critical systems, through the use of the maximum degree of automation, especially in respect of code generation and verification. An outstanding property of SACRES is the combination of specification styles and specification tools being applied in practice with automatic tools to establish provable correctness with respect to required properties. Both dependability and productivity are increased by automatic code generation from high-level specifications such that the generated code can be validated against higher levels by rigorous proofs. These techniques allow traditional tests by sampling to be replaced by rigorous checking techniques which correspond to 100% coverage of test cases. In order to address a global innovative approach in the near future which match the whole software configuration, the SACRES tool set should be interfaced with asynchronous techniques matching the operating system development. This raises an open question in the software development future new process.

This paper describes an experimental study to compare the various steps involved in Hidden Markov Model (HMM) and Hidden Semi Markov Model (HSMM) approaches for recognition and synthesis, respectively. It presents different aspects of the two systems, bringing up the commonalities and differences among them. Further, to demonstrate the usefulness of Markov models, an HMM based recognition system and HSMM based synthesis system are implemented for Assamese handwritten numerals. All the experiments are carried out by using Assamese numeral data written by native writers. The experimental result proves the potential of Markov model applied to both handwriting recognition and synthesis system.

Model-Based Development (MBD) provides an additional level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic treatments of these models with dedicated tools like synthesis of system's application by automatic code generation. Real-Time and Embedded Systems (RTES) are often constrained by their environment and/or the resources they own in terms of memory, energy consumption with respect to performance requirements. Hence, an important problem to deal with in RTES development is linked to the optimization of their software part. Although automatic code generation and the use of optimizing compilers bring some answers to application optimization issue, we will show in this paper that optimization results may be enhanced by adding a new level of optimizations in the modeling process. Our arguments are illustrated with examples of the Unified Modeling Language (UML) state machines diagrams which are widely used for control aspect modeling of RTES. The well-known Gnu Compiler Collection (GCC) is used for this study. The paper concludes on a proposal of two step optimization approach that allows reusing as they are, existing compiler optimizations.

With the emergence of approximate computing as a design paradigm, many approximate functional units have been proposed, particularly approximate adders and multipliers. These circuits compromise the accuracy of their results within a tolerable limit to reduce the required computational effort and energy requirements. However, for an ongoing number of such approximate circuits reported in the literature, selecting those that minimize the required resources for designing and generating an approximate accelerator from a high-level specification, while satisfying a defined accuracy constraint, is a joint high-level synthesis (HLS) and design space exploration (DSE) challenge. In this paper, we propose a novel automated framework for HLS of approximate accelerators using a given library of approximate functional units. Since repetitive circuit synthesis and gate-level simulations require a significant amount of time, to enable our framework, we present AxME, a set of analytical models for estimating the required computational resources when using approximate adders and multipliers in approximate designs. We propose DSEwam, a DSE methodology for error-tolerant applications, in which analytical models, such as AxME, are used to estimate resources needed and the accuracy of approximate designs. Furthermore, we integrate DSEwam into an HLS tool to automatically generate Pareto-optimal, or near Pareto-optimal, approximate accelerators from C language descriptions, for a given error threshold and minimization goal. We release our DSE framework as an open-source contribution, which will significantly boost the research and development in the field of automatic generation of approximate accelerators.

Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. This paper describes an important extension of an existing architectural synthesis system (AMICAL) targeting the generation of microcoded for ASIP controllers. The designer can then generate both style of architecture, hardwired and programmable, using the same synthesis system and can quickly evaluate the trade-offs of hardware decisions.

Failure to validate the Health Survey for England physical activity module in a cardiac population

IntroductionH pylori is usually acquired mostly in childhood and leads to prolonged exposure to this potentially carcinogenic agent.AimThe aim of this study was to evaluate the accuracy of invasive diagnostic...

In order to realize the verification of the standard platinum resistance thermometer in the temperature zone from 0°C to 419.527°C and the calculation of the reference table, a system for the verification data processing of the standard platinum resistance thermometer and the automatic generation of any reference table was developed based on PyQt5. The system includes three parts: the standard platinum resistance information input interface, the verification result output interface, and the automatic generation interface of the reference table. After the calculation is completed, the Excel format verification report can be automatically generated. The experimental results are compared with the reference function table data in the temperature zone from 0°C to 419.527°C in the verification regulations, and the results meet the requirement that the difference between the two calculation results is less than <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1\times 10^{-8}$</tex> , which proves the reliability of the calculation results of the system. Compared with the traditional calculation relying on Excel table, the verification operation of this system is clearer. The division value and final temperature of the platinum resistance thermometer scale can be customized to verify, and the design interface is friendly and the operation is simple, which greatly improves the working efficiency of the metrology personnel for the verification. This method can be used for the verification of first-class and second-class standard platinum resistance.