Solder Voiding in Assemblies Using Via-In-Pad Ball Grid Array Design

The impact of voiding on BGA (Ball Grid Array) solder joint reliability has been a debatable topic for some time. It is believed that certain categories of voiding do not significantly affect the reliability of the solder joints and that voiding is preferred and acceptable to a certain extent. The reason for this is that voids are believed to change the direction of, or halt the propagation of cracks and thereby improve the reliability of the solder joint. However, excess voiding is considered to aggravate the solder joint failure. The formation of voids can be attributed to different process parameters – surface contamination and moisture absorption in BGAs and Printed Circuit Boards (PCBs), solder paste & operating conditions and reflow profiles – to mention a few. Among these, the reflow profile is one of the very critical parameters in electronics manufacturing. Several experiments have been conducted in the past to study the impact of reflow profile. In addition, the electronics manufacturing industry is gradually moving towards a lead-free environment. This has resulted in higher peak temperatures for the reflow profiles. However, with higher peak temperatures, the other reflow parameters also have to be varied. An optimum range for all the reflow parameters would reduce (or even eliminate) the formation of solder voids. This paper investigates the impact of the reflow profile on the quality of the lead-free surface mount solder joint. In particular, the impact of the reflow profile on solder joint voiding for lead-free assemblies is analyzed. The critical reflow profile parameters that are responsible for voiding such as preheat temperature, ramp-up rate, and peak temperature were varied within the allowable process limits to verify if the voiding could be minimized. Ball Grid Arrays (BGAs) were assembled using varying reflow profiles. The analysis involved x-ray examination to observe the formation of solder voids.

There are no criteria for Bottom Terminal Component (BTC) solder void except 30% area for BGA solder joints in IPC-A-610F. It means supplier and customer should co-define the criteria for their own products. The solder void ratio control is related to many factors including PCB surface treatment, component soldering terminal condition, solder paste selection, footprint design, stencil aperture design, reflow profile, etc. In this paper, we focus on System in Package (SiP) modules including molding and metal lid types to investigate the impact of void inside BTC solder joint post reflow. The parts include Crystal and QFN that only have solder joint beneath component body. Firstly, to confirm the solder void ratio changes before and after reflow of pre-condition test, humidity absorbing then passing 3 times reflow. Secondly, keep monitoring the reliability test result after Thermal Cycling (TC), Unbiased Highly Accelerated Stress Test (UHAST) and Temperature Humidity Bias (THB). From the data collection known, solder void changed during reflow of pre-condition. Even if the solder void become larger, the solder joint reliability still not become worse and passed all the test items and cycles. It means the risk of BTC solder void won't cause reliability issue in our cases even the void reach 60%. According to this investigation, we don't need to scrape the samples with larger void before reliability test but follow up the test result. This way, we won't waste time and money for re-building a lot for reliability. Furthermore, since the solder joint void had been qualified by reliability test, we can set up a wider window for in-process quality control.

A thermo-mechanical loading system, which can superimpose a temperature and location dependent strain on solder joints, is proposed in order to conduct highly accelerated thermal-mechanical cycling (HATC) tests to assess thermal fatigue reliability of Ball Grid Array (BGA) solder joints in microelectronics packages. The application of this temperature and position dependent strain produces generally similar loading modes (shear and tension) encountered by BGA solder joints during service, but substantially enhances the inelastic strain accumulated during thermal cycling over the same temperature range as conventional ATC (accelerated thermal cycling) tests, thereby leading to a substantial acceleration of low-cycle fatigue damage. Finite element analysis was conducted to aid the design of experimental apparatus and to predict the fatigue life of solder joints in HATC testing. Detailed analysis of the loading locations required to produce failure at the appropriate joint (next to the die-edge ball) under the appropriate tension/shear stress partition are presented. The simulations showed that the proposed HATC test constitutes a valid methodology for further accelerating conventional ATC tests. An experimental apparatus, capable of applying the requisite loads to a BGA package was constructed, and experiments were conducted under both HATC and ATC conditions. It is shown that HATC proffers much reduced cycling times compared to ATC.

In the surface mount technology, Ball Grid Array (BGA) has been used in a production of PC boards, because of their excellent characters such as high density of the lead pin pitch, better lead rigidity and self-alignment during re-flow processing. This paper deals with the development of image analysis for the detection of defects at BGA solder joints in PC boards by using X-ray images. In the conventional IC boards, it is possible to detect defects of solder joints by visual inspection, because the lead of IC package is set on its outside. However, we can't detect visually defects at BGA solder joints, because they are hidden under the IC package. In a production line, the inspection of BGA in PC boards depends on the function test of electric circuits in the final process. To improve a cost performance and the reliability of PC boards, an inspection of BGA is required in the surface mount process. Types of defects at BGA solder joints are solder bridge, missing connection, solder voids, open connection and miss-registration of parts. As we can find mostly solder bridge in these defects, we pick up this to detect solder bridge in a production line. The problems of image analysis for the detection of defects at BGA solder joints are the detection accuracy and image processing time according to a line speed of production. To get design data for the development of the inspection system, which can be used easily in the surface mount process, it is important to develop image analysis techniques based on X-ray image data. At the first step of our study, we attempt to detect the characteristic of the solder bridges based on an image analysis.

Numerical simulation and fatigue life estimation of BGA packages under random vibration loading

This study is part three in a series of papers on voiding in solder joints and methods for mitigation of voids. In this study several new variables were tested and compared to previous data on voiding. A new circuit board design was used which is different than the circuit board used in previous studies. The new circuit board design includes two sizes of QFNs (Quad Flat No Lead), BGA's (Ball Grid Array), and LGA (Land Grid Array) components which are susceptible to voiding. The following variables were evaluated with respect to voiding: Solder powder size was varied using a no-clean lead-free solder paste and IPC Type 3, Type 4 and Type 5 SAC305 solder powders. Solder alloy was studied using SAC305 alloy, SN100C® alloy, SN100CV® alloy and a mixture of SAC305/SN100C alloys. Surface finish on the circuit board is thought to have an impact on voiding. Organic solderability preservative (OSP) surface finish is more difficult to wet with solder than other surface finishes and in theory should produce higher voiding levels, and this was evaluated with multiple solder pastes. The performance of a new “low voiding” no clean solder paste was compared to other industry standard no clean solder pastes. Several new stencil designs on QFN thermal pads were tested. Data was gathered and statistical analysis performed to compare and contrast the voiding data. What was learned from this work is summarized below: Solder powder particle size affects voiding for some solder pastes. Voiding tends to decrease as solder powder size becomes smaller. Solder alloy affects voiding and seems to follow a trend with melting range. Wider melting ranges tend to generate lower voiding levels. Organic solderability preservative (OSP) surface finish gave higher voiding than electroless nickel immersion gold (ENIG) surface finish for a no clean lead free solder paste that was tested. Two different water soluble lead free solder pastes showed similar voiding levels for OSP and ENIG finishes. New “low voiding” solder pastes are becoming more common in our industry. In this work, low voiding solder paste F showed lower voiding than an industry standard solder paste C. Stencil design has an impact on voiding. In this study, area of printed solder paste coverage was varied. Voiding levels were much higher for 50 to 60% solder paste coverage than for 70 to 80% solder paste coverage. Based on the results of this work, the following recommendations were made to reduce voiding. Use of smaller solder powder sizes can reduce voiding with certain types of solder paste. Use of specific solder alloys may help mitigate voiding. Use a solder paste that works well with the surface finish to minimize voiding. Use “low voiding” solder pastes to reduce the overall potential for voiding. Optimize the stencil design for the components to allow for complete wetting and gas escape routes. Applying these recommendations may create issues on the printed circuit board assembly (PCBA). For example, use of smaller solder powder particle sizes may lead to increased random solder balling and/or graping. Increasing the volume of printed solder paste may lead to bridging for micro BGA and ultra-fine pitch components. Reduction of voiding may be important enough to risk these potential issues. This is left to the reader's judgement. It is the intent of this work to analyze general trends in voiding and give recommendations to help the reader to “Fill the Void.

A extraction approach is proposed based on an image processing in order to improve the accuracy of 2D quality information extraction for surface mount technology (SMT) BGA(Ball Grid Array) solder joint of chip components. First, some appropriate image processing algorithms are utilized to eliminate the noise in the solder joint image. And a binaryzation image is obtained after character. Then the BGA Solder Joint 2D quality information extraction system is developed based on Visual C++, and the 2D quality information of solder joint circumference, area, void area, and diameter, are obtained. The experimental results have illustrated that the system can accomplish a good extraction result.

Accelerated temperature cycling (ATC) was used to assess the thermal fatigue reliability of a Pb free, 37.5 mm fully populated, 1295 I/O ball grid array (BGA) package assembled with backward compatible or mixed alloy (Pb free BGA/SnPb paste) processing. The Pb-free BGA components were fabricated with Sn-4.0Ag-0.5Cu (SAC 405) solder balls. The surface mount assembly was done using several custom SnPb eutectic soldering profiles designed to produce different levels of Pb mixing in the BGA solder balls. The test program also included SAC405-SAC405 assemblies for reliability comparisons. The temperature cycling and metallographic data indicate that assembly parameters that produce the lowest level of Pb mixing degrade the solder joint fatigue reliability. Failure analysis demonstrates that the lower reliability is due to poorly formed solder joints resulting from incomplete reflow. The failed solder joints exhibit inadequate BGA ball collapse, minimal Pb mixing, and fatigue failure at the printed circuit board (PCB) side of the joints instead of the package-side fatigue failures that are typical for ATC testing. The test cells with more complete Pb mixing and the pure Pb-free test cell exhibited better fatigue reliability. However, failure analysis of these samples revealed that the data were compromised by the occurrence of a second failure mode in plated through hole vias that were incorporated into the PCB test vehicle. The presence of mixed mode failures (solder joint and via) precluded direct quantitative comparisons among all the test cells. The results are discussed within the context of previously published test results from the literature, including the impact of the contribution of via failures. Recommendations are outlined for additional testing to quantify the relationships between Pb mixing level and Pb-free reliability for this high density BGA package.

There has been a dramatic proliferation of research concerned with thermal stress in electronic package for the last three decades. Moreover, reviewing the mechanical bending during printed circuit board (PCB) assembly has become important in the reliability assessment of modern electronic systems. The primary research demonstrates that the assessment approach can be applied successfully to the design model of a ball grid array (BGA) package with a more complete and accurate assessment model for solder joint fatigue life under mechanical bending. Previous research has focused mostly on the thermal analysis in electronic packages; however, most modern portable electronic products used in mobile devices, personal digital assistants, and aircraft have to endure extreme environments that involve not only thermal but also mechanical bending conditions. Initially, mechanical bending tests were conducted to demonstrate the reliability of the electronic packaging during the manufacturing and shipping process. Currently, the microelectronic packaging faces mechanical bending when everyone uses his or her Smartphones. The mechanical bending occurs when the user touches the screen on the Smartphone. Therefore, interest in the mechanical bending of BGA packaging has increased with the uptake in mobile device use. In this research, the analytical solution and finite element analysis (FEA) are both presented to investigate the solder joint fatigue life. The analytical solution is presented for a PCB assembly subjected to mechanical bending by taking the axial stress, shear stress, and moment of the solder joints with discontinuity function into account. A FEM is proposed to analyze the solder joint fatigue life and to investigate the reliability of solder joints in BGA packaging subjected to mechanical bending.

The conversion to lead-free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity of pad cratering in Printed Circuit Boards (PCBs) [1, 2]. In general, lead-free solder joints are stiffer than tin-lead solder joints, and some lead-free compatible PCB dielectric materials are more brittle than conventional tin-lead compatible PCB materials. These two factors, coupled with the higher peak reflow temperatures for lead-free assembly, could transfer more strain to the PCB dielectric structure, causing a cohesive failure underneath the BGA corner pads. The likelihood of pad cratering occurring in any given assembly depends on several factors including, but not limited to the BGA package size, construction and surface finish; and the PCB pad size, material and surface finish. Standard assembly level bend and shock tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures. However, with these standard assembly level tests, it is difficult to determine if the failures occur due to a weaker PCB structure or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes. In this study, an easy-to-implement test method is presented in detail, along with calibration and test results comparing a broad spectrum of PCB attributes. Different dielectric materials and pad sizes were evaluated to develop a comparative metric that can be used to rank-order different material/pad size combinations. The results were generated over different pull temperatures and multiple reflows, to study the effect of temperature on dielectric mechanical strength characteristics. Ultimately, these metrics can be used to optimize PCB design, thus mitigating pad cratering potential.

The use of Ball Grid Array (BGA) interconnects utilizing the BGA solder joint has grown rapidly because of its small volume and diversity of its application. Therefore, the continuous quantification and refinement of BGA solder joint in terms of its reliability are required. The creep and cyclically applied mechanical loads generally cause metal fatigue on the BGA solder joint which inevitably leads to an electrical discontinuity. In the field application, the BGA solder joints are known to experience mechanical loads during temperature changes caused by power up/down events as the result of the Coefficient of Thermal Expansion (CTE) mismatch between the substrate and the Si die. In this paper, extremely small resistance changes in the lead free joints corresponding to the through-cracks generated by the thermal fatigue were measured and the failure was defined in terms of anomalous changes in the joint resistance. Furthermore, the reliability of BGA solder joints under thermal cycling was evaluated by using a criterion that may define and distinguish a failure in the solder joint. Any changes in circuit resistance according to the accumulated damage induced by the thermal cycling in the joint were recorded and evaluated by the First Order Reliability Method (FORM) procedure in order to quantify the reliability of solder joint. The first order Taylor series expansion of the limit state function incorporating with thermal fatigue models is used in order to estimate the failure probability of solder joints under heated condition. Various thermal fatigue models are utilized in this study. Models based on various plastic-strain rates such as Coffin-Manson fatigue model, total strain fatigue model and Solomon fatigue model are utilized in this study. The effects of random variables such as the CTE, the pitch of solder joint, the diameter of solder joint, and the CTE difference solder joints on the failure probability of the solder joint are systematically investigated by using a failure probability model with the FORM.

After reflow of Sn-3.8Ag-0.7Cu and Sn-20In-2Ag-0.5Cu solder balls on Au/Ni surface finishes in ball grid array (BGA) packages, scallop-shaped intermetallic compounds (Cu0.70Ni0.28Au0.02)6Sn5 (IM1a) and (Cu0.76Ni0.24)6(Sn0.86In0.14)5 (IM1b), respectively, appear at the interfaces. Aging at 100°C and 150°C for Sn-3.8Ag-0.7Cu results in the formation of a new intermetallic phase (Cu0.70Ni0.14Au0.16)6Sn5 (IM2a) ahead of the former IM1a intermetallics. The growth of the newly appeared intermetallic compound, IM2a, is governed by a parabolic relation with an increase in aging time, with a slight diminution of the former IM1a intermetallics. After prolonged aging at 150°C, the IM2a intermetallics partially spall off and float into the solder matrix. Throughout the aging of Sn-20In-2Ag-.5Cu solder joints at 75°C and 115°C, partial spalling of the IM1b interfacial intermetallics induces a very slow increase in thickness. During aging at 115°C for 700 h through 1,000 h, the spalled IM1b intermetallics in the solder matrix migrate back to the interfaces and join with the IM1b interfacial intermetallics to react with the Ni layers of the Au/Ni surface finishes, resulting in the formation and rapid growth of a new (Ni0.85Cu0.15)(Sn0.71In0.29)2 intermetallic layer (IM2b). From ball shear tests, the strengths of the Sn-3.8Ag-0.7Cu and Sn-20In-2Ag-0.5Cu solder joints after reflow are ascertained to be 10.4 N and 5.4 N, respectively, which drop to lower values after aging.

The trend towards ultra-miniaturization, high interconnection densities with minimal power consumption at low cost is driving the need for large, thin, high-stiffness substrate technologies. Glass substrates have emerged as a promising alternative to organic and silicon interposer packages due to their tunable coefficient of thermal expansion (CTE), high dimensional stability and surface smoothness, outstanding electrical properties and low-cost panel-level processability. This paper presents a comprehensive study of the effect of glass CTE on board-level reliability of 100µm-thick glass ball grid array (BGA) packages, 18.5 mm x 18.5 mm in body size, with considerations of yield, warpage and thermal cycling performance. Polymer collars and novel doped solder alloys were also introduced to further enhance board-level reliability, and subsequently demonstrate the extendibility of direct SMT assembly of glass BGA packages to even larger body sizes. The test vehicle used in this study was an emulator of a single-chip application processor package. Daisy chain test dies, 10mm x 10mm in size and 100-200µm in thickness, were assembled onto the fabricated glass substrates with Si-matching CTE (3.8ppm/K) and board-matching CTE (9.8ppm/K) by dip-flux thermo-compression bonding with capillary underfill, at panel level. A stencil-based paste printing process was developed and optimized for panel-level balling of the glass packages with 250µm BGA at 400µm pitch. Variations in solder alloys were considered, including standard SAC105 and SAC305 used as reference, and the novel Mn-doped SACm by Indium Corporation. After singulation by laser dicing, the glass packages were finally mounted on mother boards by standard SMT reflow, after optimization of the heating profile to minimize solder voiding. Board-level yield was evaluated to 91%, and explained based on Shadow-Moire warpage measurements, showing a strong dependence to the chip-level underfill fillet size. Initial thermal cycling reliability was conducted on the glass BGA packages with and without polymer collars. All samples passed 600 cycles with stable daisy chain resistances, regardless of the glass CTE and solder alloy composition.

The popularity of Ball Grid Array (BGA) has been gaining momentum in the past few years. From a board assemblers' perspective, BGA offers a wide process window and low process defect rate. In the early years, the reliability of the BGA solder joints was a concern because the BGA joints are non-compliant in comparison to the joints of gull-wing QFPs. Since then many finite element analysis (FEA) and reliability studies have been published demonstrating that BGA solder joints can have adequate reliability against the shear stress caused by the mismatch of coefficient of thermal expansion (CTE). Another mode of BGA joint failure, which has not been discussed as much, is the flexure-induced failure. In a typical electronics manufacturing environment, the printed circuit boards are handled many times after surface mount and wave soldering. Hand soldering, rework, in-circuit test, functional test, and final assembly are just some of the processes before the product is eventually shipped. Most of these processes can cause bending or warping of the printed circuit assembly (PCA), On a PCA, the areas under and adjacent to the BGA components are relatively rigid compared to the rest of the board. Hence, with the same amount of board flexing, the BGA solder joints become more susceptible to fracture compared to other surface mount devices. This study employed thermal cycling, dye-penetrant test, cross-sectioning, highly accelerated life test (HALT, thermal/vibration test), highly accelerated stress auditing (HASA, thermal/vibration test), “sticky probe” with in-circuit test (ICT) fixture and strain gage measurement to investigate the failure mechanism, and to determine the effects associated with board flexure. It was discovered that excessive flexing of PCA does cause catastrophic BGA solder joint cracking. Localized board flexure during in-circuit test was found to be very high and detrimental. BGA solder joints can crack during the in-circuit test and result in opens or intermittent failures. The ICT fixture should be carefully designed and manufactured to minimize local board warp around the BGA components. A FEA tool to analyze the localized strain on the PCA can be very helpful in ICT fixture design.

A nonlinear finite element analysis was carried out to investigate the viscoplastic deformation of solder joints in a ball grid array (BGA) package under temperature cycling. The effects of constraint on print circuit board (PCB) and stiffness of substrate on the deformation behaviour of the solder joints were also studied The results indicated that high inelastic strain was developed in the joints close to the package center. On the other hand, high constraint was associated with the joint closest to the edge of the silicon chip. Increasing external constraint on the PCB caused a slight increase in stress triaxiality in the joint closest to the edge of silicon chip. There was an increase of inelastic strain in the solder joints with increasing the Young's modulus of the substrate.