Solving the chiplet placement problem via accelerated perturbed ADMM

The problem of optimal placement of elements of electrical and electronic circuits is considered. The minimum weighted length of the connections is selected as the criterion. The scheme is defined by a matrix of connections. We consider a fixed set of element positions and a distance matrix based on an orthogonal metric. This problem is a variant of the general mathematical model, called the quadratic assignment problem. The geometric limitation of the problem is that no more than one element is placed in one cell. Combinatorial analogs of the Gauss-Seidel method, the genetic algorithm, and the corresponding hybrid methods for solving the quadratic assignment problem with optimal placement of electronic equipment elements are developed and implemented on a computer. A series of computational experiments was conducted, which showed satisfactory computational qualities of the proposed methods. The proposed computational method, which is a combinatorial analog of the method of coordinate descent and one of the variants of the general approach based on paired permutations, is characterized by the best computational qualities among the methods studied in the article. According to well-known studies, the genetic algorithm is obviously no worse than the Monte Carlo method. The research conducted in the article shows that the method of penalty functions in the problem of placement and for the case of a genetic algorithm is ineffective. Therefore, it is of interest to consider permutations without repetitions as individuals of the population. This circumstance is taken into account at the stages of selection and mutation: at these stages, the standard calculations according to the genetic algorithm are supplemented by the procedure of paired rearrangements of genes in the chromosome. The article provides a detailed description of the program for the implementation of the genetic method on a computer.

In this paper, a novel hybrid optimization method to solve the phasor measurement unit (PMU) placement problem is presented. The optimal PMU placement (OPP) problem is formulated to guarantee both full observability of the network and minimal number of PMUs. In the hybrid optimization method, the mechanism of simulated annealing (SA) is involved into original particle swarm optimization (PSO) to prevent the method from premature convergence; crossover and mutation operators are applied to increase the diversity of swarm. The proposed method keeps the advantage of PSO to find the optimum result quickly, and is still simple to implement, and can further improve the ability of jumping out of local optimum results. Simulation results on several IEEE systems show the effectiveness of the method. (5 pages)

In this paper we study a version of the Multidimensional Arrangement Problem (MAP) that embeds a graph into a multidimensional array minimizing the aggregated (Manhattan) distance of the embedded edges. This problem includes the minimum Linear Arrangement Problem (minLA) as a special case, among others. We propose JAM, a tabu-based two-stage simulated annealing heuristic for this problem. Our algorithm relies on existing techniques for the minimum linear arrangement (minLA) problem, which are non-trivially adapted to work in multiple dimensions. Due to the scarcity of specific benchmarks for MAP, we have tested the performance of our algorithm with benchmarks for the minLA and Quadratic Assignment Problems (with more than 80 graphs). For each graph in these benchmarks, we provide results for 1, 2 and 3-dimensional instances of MAP, enlarging, hence, the benchmarking resources for the research community. The results obtained show the practicality of JAM, often matching the best known result and even improving some of them.

SYNOPTIC ABSTRACTThis paper introduces the placement problem that arises in the established standard-cell-style design of integrated circuit (IC) parts, and reports on a method for effectively solving this problem. The placement problem is to assign geometric coordinates on the two-dimensional IC “chip” to its many small, predesigned logic functions (standard cells). Applying a practical, simulated-annealing search to the critical placement problem as part of designing an IC can have a surprisingly large impact on a part's cost and manufacturability.Results from a recent benchmarking contest illustrate the importance of effectively solving the placement problem, and support the effectiveness of the methods introduced in this paper. The new solution method applies simulated-annealing search using an approximate placement model (considering only bounding boxes of the logical nets, and considering only approximate, fixed-grid carrier locations for the cells that define the boxes), adaptive wiring congestion ...

This paper concerns the problem of placing components on a circuit board, in such a way that a predefined set of objectives is optimized. The layout of integrated circuits motivated the use of hierarchical techniques as a means of dealing with increasing circuit complexity. A fully hierarchical approach to the placement problem is here described, based on a tree structure which embodies an adopted set of circuit properties and objective functions. The tree structure represents the relative positions of a hierarchy of blocks of components on the board surface.

The paper discusses a modified algorithm based on the ants’ behavior in nature. We suggest to apply this algorithm for solving the element placement problem—one of the most difficult problem in the VLSI design. This problem belongs to the NP-class problem that is there are no precise methods to solve this problem. Also we formulate the placement problem and choose an optimization criterion. The developed ant colony optimization (ACO) algorithm obtains optimal and quasi-optimal solutions during polynomial time. The distinguish feature of the algorithm is that alternative solution are represented as an undirected graph with weighted edges. Besides, at each generation the algorithm creates a taboo-list to eliminate the quantity of agent (ant) which is wrong from the point of view the using of Reverse Polish notation. To compare obtained results with known analogous algorithms we developed software which allows to carry out experiments on the basis of IBM benchmarks. Conducted experiments shown that the ACO algorithm is better than the other algorithms an average of 9 %.

With the development of the vehicular communications technology, roadside units (RSUs) placement problem has recently received considerable attentions in vehicular ad hoc networks (VANETs). This paper addresses the roadside units (RSUs) placement problem for traffic flow coverage requirement number in vehicular ad hoc networks (VANETs). Given a set of road segments, some traffic flows and a coverage requirement number n, the problem is how to find the optimal placement of RSUs, such that each traffic flow is covered by at least n RSUs. We first investigate full RSUs placement problem, which place all the RSUs on the given road segments totally. We prove that this problem is NP-hard. Then, we propose a greedy algorithm to solve the problem and theoretical analysis is given. We also study incremental RSUs placement problem, which place the partial RSUs based on the deployed RSUs on the given road segments. Based on the proposed greedy algorithm, we also propose a algorithm to solve the incremental RSUs placement problem. Extensive simulations have been conducted to show the performance of our proposed algorithms is superior to the other algorithms.

We consider the placement of FPGA designs with multiple I/O standards on modern FPGAs that support multiple I/O standards. We propose an efficient approach to solve the constrained I/O placement problem by 0-1 integer linear programming within a high performance placement flow. We derive an elegant 0-1 integer linear program formulation which is applicable not only for devices with symmetric I/O banks but also for devices with asymmetric I/O banks (i.e., different banks may have different sizes and/or support different subsets of I/O standards). Moreover, it is capable of handling user's prelocked I/Os. We also show that additional restrictions such as conditional usage of V/sub ref/ pins can be easily incorporated. Our formulation involves only a small number of 0-1 integer variables independent of the device size or the number of I/O objects, hence our approach can comfortably handle very large problem instances. Extensive experimentation showed that the 0-1 integer linear program corresponding to a feasible instance of the constrained I/O placement problem can be solved in seconds.

The Wells Placement Problem (WPP) consists in choosing well locations within an oil reservoir grid to maximize the reservoir total oil production, subject to distance threshold between wells and number of wells cap constraints. A popular approach to WPP is Genetic Algorithms (GA). Alternatively, WPP has been approached in the literature through Mathematical Optimization. Here, we conduct a computational study of both methods and compare their solutions and performance. Our results indicate that, while GA can provide near-optimal solutions to instances of WPP, typically Mathematical Optimization provides better solutions within less computational time.

Several novel topological representations of non-slicing floorplans have been more recently proposed, providing new ideas and techniques for solving block placement problems and other related layout applications. Among these topological representations, ordered trees exhibit a lower redundancy and, therefore, a provable smaller search space, which makes them the best topological candidate for solving general block placement problems. Starting from the early eighties, binary trees have been widely used to represent slicing floorplans. This paper shows that binary trees can efficiently model non-slicing floorplans as well, as there is a one-to-one mapping between the sets of binary and ordered trees representing the floorplan. Moreover, this paper shows that binary trees exhibiting a certain property can be used to represent block placement configurations with symmetry constraints, which is very useful when dealing with device-level placement problems for analog layout. As the number of these trees is proven to be smaller than the number of symmetric-feasible sequence-pairs, using binary trees is better than using either sequence-pairs or O-trees when solving analog placement problems. A comparative evaluation, substantiating these theoretical results, has been carried out by providing alternative optimization engines to a placement tool operating in an industrial environment.

OPTIMAL SENSOR/ACTUATOR PLACEMENT FOR ACTIVE VIBRATION CONTROL USING EXPLICIT SOLUTION OF ALGEBRAIC RICCATI EQUATION

The paper deals with a hybrid algorithm to solve one of the main problem of the VLSI design - the placement problem. This problem is NP-complete and does not have a deterministic algorithm for its solution. Hence, the development of new search methods is an urgent task. Among a variety of probabilistic methods, bioinspired algorithms have already shown its effectiveness for combinatorial optimization problems solving. The paper presents a hybrid bioinspired algorithm for VLSI fragments placement. The authors suggest an approach based on a bee algorithm at the first level for searching a diversifying and parallel genetic algorithm at the second level to provide a depth search in the vicinity of the points. The problem formulation and detailed description of algorithm steps are presented. Series of computational experiments were carried out in which theoretical dependences of obtained optimal and quasi-optimal solutions on the values of input parameters were confirmed empirically. The comparison was carried out with known analogous algorithms for VLSI fragments placement: Capo 8.6, Feng Shui 2.0, Dragon 2.23. The increase in the solutions quality is on the average 19 per cent.

Several novel topological representations of non-slicing floor-plans [2] have been more recently proposed, providing new ideas and techniques for solving block placement problems and other related layout applications. Among these topological representations, ordered trees exhibit a lower redundancy and, therefore, a provable smaller search space, which makes them the best topological candidate for solving general block placement problems. Starting from the early eighties, binary trees have been widely used to represent slicing floorplans [7]. This paper shows that binary trees can efficiently model non-slicing floorplans as well, as there is a one-to-one mapping between the sets of binary and ordered trees representing the floorplan. Moreover, this paper shows that binary trees exhibiting a certain property can be used to represent block placement configurations with symmetry constraints, which is very useful when dealing with device-level placement problems for analog layout. As the number of these trees is proven to be smaller than the number of symmetric-feasible sequence-pairs [1], using binary trees is better than using either sequence-pairs or O-trees when solving analog placement problems. A comparative evaluation, substantiating these theoretical results, has been carried out by providing alternative optimization engines to a placement tool operating in an industrial environment.

In Fog computing the placement selection of services in network devices with computational and storage features is an NP-hard problem. We analyse the design of Fog scenarios and the placement problem using Electre III a multi-criteria decision method for outranking alternatives. In this study, we model a Fog environment to apply a decision model for determining which alternatives are the most suitable in each application deployment. We compare the results with the weighted average to analyse the applicability of Electre III method in the Fog placement problem. We design a dynamical scenario in which new users appear along the simulation and we use the latency, hop count, cost, deployment penalty and energy consumption criteria to rank placement alternatives. This approach enables the study of how the characteristics of the resources have to be distributed, that is, how to design Fog scenarios, in order to make the allocation of applications more efficient.

Resumen En “Naturalismo sin representacionalismo”, Huw Price propone una variedad de naturalismo –una que él denomina naturalismo del sujeto– que supuestamente puede evitar los problemas de la localización relacionados con entidades “incómodas” como son los hechos morales, los significados, las verdades matemáticas y otras similares. A partir de una concepción expresivista de todo el lenguaje, Price defiende que los problemas de la localización descansan sobre un error categorical: el error consiste en considerar que toda oración representa algún estado de hechos mundano. En nuestro trabajo, a partir de nuestra crítica al expresivismo de Price, cuestionaremos su respuesta a los problemas de la localización. Palabras clave: Naturalismo del sujeto, representacionalismo, expresivismo global, deflacionismo, verdad. Abstract In his article “Naturalism Without Representationalism”, Price proposes a variety of naturalism –subject naturalism, as he calls it- that is supposedly able to avoid placement problems about “odd” entities such as moral facts, meanings, mathematical truths and the like. Assuming an expressivist conception about the entire language, Price argues that placement problems rest on a category mistake: the mistake of considering all sorts of sentences as representing worldly states of affairs. In this article, by arguing against Price’s expressivism, I call his response to placement problems into question. My thesis is that placement problems are genuine ontological problems. Key Words: Subject Naturalism, Representationalism, Global Expressivism; Deflationalism; Truth.