Some Studies on Optimal Specification of Read-Only Memories in Microprogrammed Digital Computers

An Instantaneous Floating Point (IFP) digitizer consists of an analog to digital converter preceded by a gain ranging amplifier and sampler. IFP digitizers are commonly used to record non-stationary signals corrupted by non-stationary noise, the signal plus noise having a large dynamic range. Statistical analysis for an arbitrary number of converter bits, number of gain bits, and gain base reveal the undesirable effects an IFP digitizer may produce. Relationships are obtained between the number of converter bits, number of gain bits, and gain base which, when satisfied, avoid these undesirable effects and cause the IFP digitizer to perform essentially as a sampler. Further application of these relationships produces a solution to the problem of finding the minimum total number of bits and their allocation between the converter and gain words.

Private information retrieval (PIR) protocols allow a user to retrieve a data item from a database without revealing any information about the identity of the item being retrieved. Specifically, in information-theoretic k-server PIR, the database is replicated among k non-communicating servers, and each server learns nothing about the item retrieved by the user. The cost of PIR protocols is usually measured in terms of their communication complexity, which is the total number of bits exchanged between the user and the servers. However, another important cost parameter is the storage overhead, which is the ratio between the total number of bits stored on all the servers and the number of bits in the database. Since single-server information-theoretic PIR is impossible, the storage overhead of all existing PIR protocols is at least 2 (or k, in the case of k-server PIR). In this work, we show that information-theoretic PIR can be achieved with storage overhead arbitrarily close to the optimal value of 1, without sacrificing the communication complexity. Specifically, we prove that all known k-server PIR protocols can be efficiently emulated, while preserving both privacy and communication complexity but significantly reducing the storage overhead. To this end, we distribute the n bits of the database among s + r servers, each storing n/s coded bits (rather than replicas). Notably, our coding scheme remains the same, regardless of the specific k-server PIR protocol being emulated. For every fixed k, the resulting storage overhead (s +r)/s approaches 1 as s grows; explicitly we have equation. Moreover, in the special case k = 2, the storage overhead is only 1 + 1/s. In order to achieve these results, we introduce and study a new kind of binary linear codes, called here k-server PIR codes. Finally, we show how such codes can be constructed from multidimensional cubic, from Steiner systems, and from one-step majority-logic decodable codes.

EVENODD(p, 3) are binary MDS array codes with p information columns and three parity columns. When an information column fails, we can recover the failed information bits by downloading some bits from p−1 surviving information columns and three parity columns. In this paper, we derive a lower bound on the total number of bits downloaded during the repair process. Moreover, we present an algorithm for the single information recovery of EVENODD(p, 3). The results show that the total number of bits downloaded during the repair process of our algorithm is less than that of the existing algorithm.

We consider the problem of maintaining a dynamic dictionary T of keys and associated data for which both the keys and data are bit strings that can vary in length from zero up to the length w of a machine word. We present a data structure for this variable-bit-length dictionary problem that supports constant time lookup and expected amortized constant-time insertion and deletion. It uses O ( m + 3 n − n log 2 n ) bits, where n is the number of elements in T , and m is the total number of bits across all strings in T (keys and data). Our dictionary uses an array A [1 … n ] in which locations store variable-bit-length strings. We present a data structure for this variable-bit-length array problem that supports worst-case constant-time lookups and updates and uses O ( m + n ) bits, where m is the total number of bits across all strings stored in A . The motivation for these structures is to support applications for which it is helpful to efficiently store short varying-length bit strings. We present several applications, including representations for semidynamic graphs, order queries on integers sets, cardinal trees with varying cardinality, and simplicial meshes of d dimensions. These results either generalize or simplify previous results.

We propose a structure for a layered light-field display composed of high-resolution binary layers and a low-resolution, multibit backlight. This structure aims to increase the upper bound of the spatial frequency while also reducing the total number of bits for the display. The increased layer resolution increases the upper bound of the spatial frequency, meaning that the display can reproduce an object with a large amount of pop-out more clearly than can a conventional light-field display. In contrast, limiting the layers’ transmittance to binary (on/off) levels reduces the total number of bits for the display, thus maintaining the high efficiency of light-field representation. The low-resolution backlight, whose pixels can take multibit values, compensates the number of intensity levels, which would otherwise be quite limited with only the binary layers. Through analytical and experimental results, we show that a display based on the proposed structure can reproduce a light field with high quality and high efficiency as a result of combining the high-resolution binary layers and low-resolution backlight.

On Data Structures and Asymmetric Communication Complexity

For many years, Herlihy’s elegant computability-based Consensus Hierarchy has been our best explanation of the relative power of various objects. Since real multiprocessors allow the different instructions they support to be applied to any memory location, it makes sense to consider combining the instructions supported by different objects, rather than considering collections of different objects. Surprisingly, this causes Herlihy’s computability-based hierarchy to collapse. In this paper, we suggest an alternative: a complexity-based classification of the relative power of sets of multiprocessor synchronization instructions, captured by the minimum number of memory locations of unbounded size that are needed to solve obstruction-free consensus when using different sets of instructions.

To the present day, the performance of microprocessors has progressed dramatically. Recently, almost all computer systems use reduced instruction set computer (RISC) architectures. However, about 30 years ago, complex instruction set computer (CISC) architectures were widely used for almost all computer systems. The advantages and successes of RISC architectures are attributable to their simplified structures. Conventional complex instruction set computer (CISC) architectures invariably included various and numerous instruction sets. Each instruction was able to execute a complicated multi-step operation. For that reason, the CISC architectures were useful in assembler-based programming environments and in systems with small amounts of memory. However, such complicated architectures prevent increases in clock frequency or a processor’s processing power. Therefore, RISC architectures—which use simple architectures based on single-step instruction sets—have been developed. The RISC architectures present advantages in terms of higher clock frequency, smaller implementation area, and lower power consumption than conventional complex instruction set computer (CISC) architectures. Observation of many examples reveals that, in circuit implementations, a simple structure is best to increase the overall performance. That principle is also applicable to programmable devices. If clock-by-clock reconfigurable devices are used, even a single instruction set computer (SISC) can be implemented onto them. A single instruction set computer is one in which a processor has only a single instruction. During production, various single instruction set computers are prepared: a single instruction set computer with an AND logic function, a single instruction set computer with an adder function, and so on. These processor units are implemented at necessary times and at necessary places of a programmable device. In CISC and RISC architectures, the hardware is fixed. Its operations are switched using software commands, as portrayed in Fig. 1(a). In contrast, in a single instruction set computer, the operation changes are executed by hardware reconfigurations, as shown in Figs. 1(b) and 1(c). Therefore, in a single instruction set computer, a processor with a certain function itself can be reconfigured to another processor with another function. The implementation of such single instruction set computers provides the following advantages under programmable device implementations. A single instruction set computer with the simplest architecture can operate at the highest clock frequency among all processor architectures. In RISC architectures, many selectors to change functions are implemented; such selectors have a certain delay. However, single instruction set computers

Very low bit rate image sequence coding is very important for video transmission and storage applications. The fundamental goal of image sequence coding is to remove spatial redundancy and only update the moving parts in an image sequence so that the total information bits required for storage or transmission can be greatly reduced. In our proposed approach, each frame within an image sequence will be separated into moving and stationary blocks. Only the moving blocks need to be transmitted to the decoder, so that the total number of bits and computing time are greatly reduced. The moving blocks will be encoded by edge-based side-match finite-state classified vector quantization (EBSMCVQ). Moreover, a quadtree can be also used to represent the moving and edge information for each frame. In order to reduce the number of bits for the quadtree, we propose a new difference quadtree technique that only transmits the different parts between the previous frame's quadtree and the current frame's quadtree. In the proposed interframe difference quadtree EBSMCVQ image sequence coding scheme, the average bit rate of each frame is reduced to 0.0393 b/pixel and the PSNR is still up to 35.40 dB for image sequence Claire.

In order to realize the information guided channel hopping, also known as spatial modulation, with more design flexibility, in this paper we propose a novel scheme that allows operation with an arbitrary number of transmit antennas. Once the number of transmit antennas is not a power of two, the antennas' symbols are mapped by different numbers of bits. Subsequently, constellations with different orders are exploited for the modulation of radiated symbols so as to guarantee that the total number of bits transmitted at each time slot remains the same. Furthermore, we introduce a decoding algorithm with low complexity for this design. Numerical results on bit error rate performance are provided and substantiate that the proposed scheme turns out to be a promising alternative to the design of information guided channel hopping. © 2012 IEEE.

This paper studies distributed (strongly convex) optimization over multi-agent networks, subject to finite rate communications. We propose the first distributed algorithm achieving geometric convergence to the exact solution of the problem, matching thus the rate of the centralized gradient algorithm (although with different constants). The algorithm combines gradient tracking with a quantized perturbed consensus scheme. The impact on the convergence (rate) of design and network parameters, such as number of bits, algorithm step-size, and network connectivity, is also investigated. Finally, numerical results validate our theoretical findings. They demonstrate the existence of an interesting trade-off among solution accuracy, convergence time and communication cost, defined as the total number of bits transmitted on one link to achieve a target solution error.

Public vs. private randomness in simultaneous multi-party communication complexity

In an mHealth remote patient monitoring scenario, usually control units/data aggregators receive data from the body area network (BAN) sensors then send it to the network or “cloud”. The control unit would have to transmit the measurement data to the home access point (AP) using WiFi for example, or directly to a cellular base station (BS), e.g. using the long-term evolution (LTE) technology, or both (e.g. using multi-homing to transmit over multiple radio access technologies (Multi-RATs). Fast encryption or physical layer security techniques are needed to secure the data. In fact, during normal conditions, monitoring data can be transmitted using best effort transmission. However, when real-time processing detects an emergency situation, the current monitoring data should be transmitted real-time to the appropriate medical personnel in emergency response teams. The proposed approach consists of benefiting of the presence of multi-RATs in order to exchange the secrecy information more efficiently while optimizing the transmission time. It can be summarized as follows (assuming there are two RATs):1) The first step is to determine the proportion of data bits to be transmitted over each RAT in order to minimize the transmission time, given the data rates achievable on each RAT. Denoting the data rates by R1, and R2, and the total number of bits to be transmitted by D = SUM(D1,D2), where D1 and D2 are the number of bits to be transmitted over RAT1 and RAT2 respectively, then they should be selected such that D1/R1 = D2/R22) Then, the exchange of the secrecy parameters between sender and receiver is done over the two RATs in order to maintain the security of the transmission. To avoid the complexity of public key cryptography, a three way handshake can be used: 2-1) The sender decides to divide the data into n parts, with a fraction n1 sent on RAT1 and a fraction n2 sent on RAT2, according to the ratios determined in 1) above (i.e. the sum of the bits in the n1 parts should be close to D1 bits, and the sum of the n2 parts should be close to D2 bits) 2-2) The sender generates a scrambling vector P(D,n) to scramble the n data parts and transmit them out of order. 2-3) The sender groups the secret information consisting of S = {n, n1, n2, P(D,n)}, and could add additional information to protect against replay attacks, e.g. timestamp, nonce, etc., and sends this information on the two RATs, encrypted by a different key: K11 on RAT1 and K12 on RAT2. Thus, {S}_K11 is sent on RAT1 and {S}_K12 is sent on RAT2. 2-4) The receiver does not know K11 and K12. Thus, it encrypts the received information with two other keys K21 (over RAT1) and K22 (over RAT2) and sends them back: {{S}_K11,K21} is sent on RAT1 and {{S}_K12,K22} is sent on RAT2. 2-5) The sender decodes the received encrypted vectors using his keys and sends back {S}_K21 on RAT1 and {S}_K22 on RAT2. The secret information is still securely encoded by the receiver's secret keys K21 and K22. 2-6) The receiver can now decrypt the information and obtain S. 3. The two parties can now communicate using the secret scrambling approach provided by S. This information can be changed periodically as needed. For example, if the data is subdivided over 10 parts, with 40% to be sent over LTE and 60% to be sent over WiFi, according to the scrambling vector P(D,n) = {4,1,10,7,3,9,5,2,6}, then parts {4,1,10,7} are sent over LTE and parts {7,3,9,5,2,6} are sent over WiFi. The receiver will sort them out in the correct order.

Unsurprisingly, the Android operating system runs on computer hardware. Developers for other mobile platforms can rely on supporting a single CPU architecture, instruction set, and GPU type. Android developers do not have this luxury if they would like to maximize the reach of their apps.KeywordsAndroid PlatformAndroid Operating SystemHide Surface RemovalUnique Selling PointDeferred RenderingThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper, we propose a software shared virtual memory (SVM) system for heterogeneous multicore accelerator clusters with explicitly managed memory hierarchies. The target cluster consists of a single manager node and many compute nodes. The manager node contains a generalpurpose processor and larger main memory, and each compute node contains a heterogeneous multicore processor and smaller main memory. These nodes are connected with an interconnection network, such as Gigabit Ethernet. The heterogeneous multicore processor in each compute node consists of a general-purpose processor element (GPE) and multiple accelerator processor elements (APEs). The GPE runs an OS and the multiple APEs are dedicated to compute-intensive workloads. The GPE is typically backed by a deep on-chip cache hierarchy and hardware cache coherence. On the other hand, the APEs have small explicitly-addressed local memory instead of caches. This APE local memory is not coherent with the main memory. Different main and local memory units in the accelerator cluster can be viewed as an explicitly managed memory hierarchy: global memory, node local memory, and APE local memory. Since coherence protocols of previous software SVM proposals cannot effectively handle such a memory hierarchy, we propose a new coherence and consistency protocol, called hierarchical centralized release consistency (HCRC). Our software SVM system is built on top of HCRC and software-managed caches. We evaluate the effectiveness and analyze the performance of our software SVM system on a 32-node heterogeneous multicore cluster (a total of 192 APEs).