Space-vector-based hybrid pulse width modulation technique to reduce line current distortion in induction motor drives

This paper proposes a hybrid pulse width modulation (PWM) based field weakening control strategy for a hybrid-inverter-driven open-winding (OW) permanent magnet synchronous motor (PMSM) system. The hybrid-inverter consists of two voltage source inverters, one is connected to a dc voltage source and named as main inverter (MI), and the other is connected to a floating capacitor and called compensation inverter (CI). A novel hybrid PWM technique is proposed for the hybrid-inverter, in which a double-vector-based PWM is applied to the MI to reduce the switching frequency, and the conventional space vector PWM is applied to the CI to compensate the reactive power. Furthermore, a field weakening (FW) control strategy based on the hybrid PWM technique is proposed to better utilize the dc-link voltage and extend the operation range of the OW-PMSM system. Simulation and experimental studies are carried out to verify the high efficiency and wide speed range of the proposed strategy.

Multilevel inverters have gained significant attention in recent years due to their ability to achieve higher voltage and lower harmonic distortion compared to conventional two-level inverters. Pulse width modulation (PWM) techniques play a crucial role in controlling multilevel inverters by generating the required switching signals for their power electronic devices. This paper presents a comprehensive comparative analysis of various PWM techniques employed in multilevel inverters, including sinusoidal pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), carrier-based pulse width modulation (CBPWM), and selective harmonic elimination (SHEPWM). Each PWM technique's advantages, limitations, and suitability for different multilevel inverter topologies are discussed. Furthermore, recent advancements and hybrid PWM techniques are also examined to explore potential improvements in performance and efficiency. This paper aims to provide researchers, engineers, and practitioners with valuable insights into selecting the most appropriate PWM technique for their specific multilevel inverter applications, considering factors such as performance requirements, cost constraints, and ease of implementation.

This paper presents a new Pulse Width Modulation (PWM) technique for Z-source or Impedance Source Inverter (ZSI or ISI). The proposed technique is based on the Bus Clamping PWM (BCPWM) technique for Voltage Source Inverter (VSI). The effectiveness of the proposed technique is achieved by MATLAB simulation of a ZSI. It has been observed that the proposed technique gives better performances as compared to Conventional Space Vector PWM (CSVPWM) at high modulation index and at same switching frequency like reduction in load current ripple and reduction in voltage stress across the switches. Further the proposed technique ensures less switching loss as compared to CSVPWM at same carrier frequency.

Multilevel inverters are increasingly being used in high-power medium voltage industrial drive applications due to their superior performance compared to conventional two-level inverters. Thre are a number of Pulse width modulation (PWM) techniques applied in recent years. The most widely applied PWM techniques are Sine Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM). SPWM is the most simple modulation technique that can realize easily in analog circuit. However, it has some drawbacks such as higher total harmonic distortion (THD), lower effective DC utilization and lower switching frequency. Space vector pulse width modulation (SVPWM) is widely used because of their easier digital realization and better DC bus utilization and lower THD. The complexity is due to the difficulty in determining the reference vector location, on times calculation, and switching states selection. This paper presents a simple SVPWM algorithm for diode clamped three level inverters based on standard two-level SVPWM which can easily determine the location of reference vector, calculate the on-times, the selection of switching states. Three level diode clamped inverter (3LDCI) using space vector modulation technique has been modeled and simulated using MATLAB/SIMULINK and Origin 6.1 with a passive R-L load that can be extended to any level. Simulation results are presented to verify the proposed SVPWM control in terms of THD. The results are compared with conventional sinusoidal pulse width modulation (SPWM) where SVPWM shows better performance than SPWM in terms of THD. DOI: http://dx.doi.org/10.11591/ijpeds.v5i1.6038

Conventional Space Vector Pulse Width Modulation (CSVPWM) uses conventional switching sequence in which near about 15 percent increment can be obtained in voltages compared to Sine Pulse Width Modulation (SPWM). But this method can be further modified into other advanced bus clamping methods called as Bus Clamping Pulse Width Modulation (BCPWM). One of those bus clamping methods is 30-Degree Split Clamp PWM method. It has all the advantages of Conventional Space Vector Pulse Width Modulation (CSVPWM) and it eliminates some disadvantages of traditional technique. In CSVPWM there are only 6 sectors and in 30Degree Split Clamping PWM these 6 sectors are further divided into sub-sectors (12) which allows for a new switching pattern. One of the major disadvantages of 3 phase CSVPWM is that the lower order harmonics of voltages and currents are comparably higher with respect to 30-Degree Split Clamp PWM. Filters can be easily designed for 30-Degree Split Clamp PWM. Even the switching losses are high in case of CSVPWM as switching occurs when the current is maximum depending on the power factor.

Low switching frequency is always used in an electric rail traction induction motor control system, in order to reduce switching losses and increase system reliability. But under low switching frequency, the conventional single pulse width modulation (PWM) technique for the whole speed region will produce a large number of harmonic components, which in turn cause motor heating, torque ripple, and other adverse effects. In this paper, a hybrid PWM technique formed by merging carrier-based asynchronous and synchronous modulation and optimal synchronous modulation is proposed to achieve low losses and total harmonics based on very low switching frequency. A simple low-cost and low-power digital signal processor (DSP) and field programmable gate array (FPGA) hybrid hardware structure is then adopted for implementing the technique, which fully utilizes advantages and resources of each processor. Total harmonic distortion of the system can hence be reduced by operating with the high-precision hybrid PWM, while not compromising the multirate and multitask processing requirements of traction control. Detailed implementations in both DSP and FPGA with high accuracy, low usage of resources, and computational burden are then described, focusing particularly at the smooth transitions among different PWM schemes. Simulations and experiments are eventually performed with results captured for validating the presented hybrid PWM technique.

This paper proposes the pulse width modulation (PWM) technique for the five-phase open-end winding induction motor (FPOEWIM) drive fed from five-phase dual inverter (FPDI) with a single dc source. The selected method gives the advantages of reduced switching losses specifically for induction motor drives working with higher power factors with the elimination of common-mode current (CMC). The method also reduces the computational burden over the processing unit. The proposed PWM technique is explained in detail with the implementation algorithm. The algorithm is used to select the proper switching states based on the reference vector location. Further, the proposed PWM technique is analyzed for the switching losses. The reduction in the switching losses is supported with the switching loss function (SLF) analysis. The SLF for the proposed PWM technique is plotted and compared with the conventional sinusoidal PWM (SPWM) technique. The presented method is simulated and the results are given. The validation of simulated results is done using the experimental results.

Modern power systems face challenges due to the increasing use of renewable energy sources. To overcome these challenges, cascaded H-bridge (CHB) static synchronized compensators (StatComs) have emerged as promising solutions. CHB StatComs offer the advantage of directly regulating grid voltage and power factor at medium and high voltage levels without the need for additional low-frequency transformers. However, in order to attain the desired medium and high voltage levels, a large number of H-bridge submodules (SMs) are required. Despite each individual SM processing a relatively low voltage, it has to carry the entire leg current. This results in significant switching loss that needs to be carefully considered to ensure thermal reliability and optimal system efficiency in CHB StatComs. Discontinuous pulsewidth modulation (DPWM) is a technique that has gained research attention for its ability to reduce switching loss. In CHB StatComs with a star configuration, DPWM is achieved by injecting a zero-sequence voltage (ZSV) between the neutral of the converter and system ground, which clamps a converter leg ac-side voltage to a fraction of its corresponding cluster voltage (sum of dc-side capacitor voltages per converter leg). The clamped converter leg stops switching, resulting in reduced switching loss. However, unlike two-level converters where a common dc-link is shared by three phases, the single-phase configuration of CHB StatComs, along with the use of floating capacitors in the dc-side of each SM, complicates the use of conventional DPWM methods. This complication is further exacerbated during grid imbalances, as the interaction between grid currents and the ZSV for DPWM can result in nonzero active power transfer to each leg, leading to divergence in cluster voltages and causing performance degradation. To solve this problem, the thesis focuses on developing advanced DPWM techniques that ensure effective cluster voltage control, even under severe grid imbalances, while simultaneously optimizing other control objectives, such as minimizing switching loss. The thesis first identifies a suitable DPWM method for CHB StatComs and analyzes its advantages in terms of capacitance reduction, switching loss reduction, enlargement of the inductive operation range, and reduction of converter voltage total harmonic distortion. The DPWM is then enhanced by considering the possibility of clamping to the zero-voltage level, providing benefits such as lower ZSV magnitude requirements and further reduction in switching loss. Subsequently, the thesis formulates DPWM as a finite-set optimization problem, proposing different cost functions to optimize the control objectives. This finite-set optimization formulation enables the embedding of cluster voltage control into DPWM implementation using model predictive control approaches, significantly enhancing the dynamical performance of CHB StatCom. The thesis evaluates the impact of the proposed DPWM methods on capacitor lifetime, highlighting the tradeoff between switching loss minimization and capacitor lifetime maximization. Finally, the thesis suggests future research directions, such as exploring increased clamping possibilities by considering the option of clamping to intermediate voltage levels. This novel concept has the potential to optimally address the aforementioned tradeoff between capacitor lifetime and converter switching loss. The thesis offers significant contributions to the field by effectively decoupling DPWM implementation from CHB StatCom cluster voltage control, making DPWM a feasible and reliable solution for next-generation CHB StatCom applications. Additionally, it introduces advanced DPWM strategies that allows the optimization of dedicated control objectives. Case studies demonstrate significant improvements when different control objectives are prioritized, such as a reduction of more than 45% in switching loss, an increase of over 10% in capacitor lifetime, an expansion of more than 50% in the inductive operation range, and a decrease of over 20% in dc capacitor capacitance compared to conventional sinusoidal pulsewidth modulation. The study of the thesis represents a crucial step towards fully leveraging the potential benefits of intelligently utilizing ZSV in CHB StatComs, thereby advancing CHB StatComs with improved reliability and efficiency performance. The findings presented in this thesis can benefit the design and operation of CHB StatComs, as well as other power system applications.

ABSTRACTThe present study explores the influence exerted by various pulse width modulation (PWM) techniques upon harmonic distortion and switching losses of a voltage source inverter. In the context of this inquiry, a generalized algorithm for variable frequency operations, inspired by continuous and discontinuous PWM is outlined in this article. The algorithm is explicitly formulated as a function of fundamental frequency and the load power factor angle with the objective of minimizing total harmonic distortion (THD) and switching losses within a specified frequency range. The algorithm is segmented into various regions of frequency, guided by the theory that each region corresponds to a distinct PWM technique that yields reduced harmonic distortion. In this article, a minimum switching loss algorithm is introduced and implemented using both BCPWM and ABCPWM techniques. The algorithm is specifically designed to minimize switching losses across the entire range of load power factor angles. The integration of switching loss algorithm with the selection of the optimal PWM technique across different frequency ranges results in reduced switching losses and harmonic distortion. This leads to a comprehensive PWM algorithm that efficiently reduces both THD and switching losses during dynamic frequency and load changes. Experimental and theoretical evidences demonstrate the efficacy of the proposed algorithm in attaining minimum harmonic distortion and reduced switching loss operation during variations in fundamental frequency and load.

Voltage Source Inverters (VSI) fed Induction Motors provide significant applications such as electric traction, evehicles etc., in the field of variable speed utilization. Whenever VSI is operated at constant switching frequency carrier pulse width modulation(PWM), the output voltage and current harmonics in the fast fourier transform (FFT) spectrum locates at switching frequency, and its integral multiples that tends to generate acoustic noises where acoustic noises are intolerable for human beings. Therefore, we propose a new PWM technique, namely modulated frequency triangular carrier-based bus clamping PWM (MFTC-BC-PWM) that derives a better spreading effect which overcomes the issue. The MFTC-BC-PWM is simulated and experimentally verified on TMS320F28379D TI controller and the experimental results depict that the magnitudes of dominant harmonic components have reduced significantly. Moreover, the results show that the inverter losses such as conduction and switching losses are much lower in the proposed technique when compared to the sinusoidal PWM and other conventional space vector PWM techniques.

This paper attempts to come up with a proposed configuration of Multilevel inverters with a lesser number of switches that are smaller in size, lesser in cost and with a higher efficiency. Designing an inverter topology with a lesser number of switches and proper control technique is the major challenge. cascaded H-Bridge (CHB) topology are more popular among the existing configurations of multilevel inverters (MLI). Even though it can produce more levels, it needs to accommodate a huge number of switches for higher levels. The focus of this paper is to reduce the number of components for the same voltage level of cascaded H- Bridge configuration. In addition to that, generating the gating pulses for the switches is difficult when there is an asymmetry in the switches. A new symmetrical series/parallel configuration is proposed with reduced switch count and the pulse width modulation (PWM) technique is implemented with digital logic to generate the required gating pulses for the switches. The total harmonic distortion (THDI) of the output current is reduced with this PWM technique. The simulation has been carried out in MATLAB/Simulink software for both R (resistive) and R-L (resistive -inductive) loads.

Advanced bus-clamping pulse width modulation (ABCPWM) techniques have been shown to outperform continuous and discontinuous (i.e. bus-clamping) pulse width modulation methods in terms of line current distortion, pulsating torque (in case of motor drives) and inverter switching loss at a given average switching frequency under certain operating conditions. These ABCPWM methods clamp a phase to a dc rail (as in discontinuous modulation) and switch another phase at twice the nominal switching frequency (unlike discontinuous modulation). The `double-switching' of the three phases in different intervals makes the implementation of such modulation schemes challenging. Further, the microcontrollers and digital signal processors available for power electronic applications are oriented towards implementation of continuous and discontinuous modulation schemes. This paper discusses the implementation of ABCPWM schemes on such processors. The features of the on-chip pulse-generation module in the digital signal processor are effectively utilized so as to avoid external hardware and to reduce the number of interrupts.

This paper presents a novel switching sequence for Space Vector Advanced Pulse Width Modulation generation for Z source inverter. The Performances of an inverter depends on what type of modulation strategies is used to switch. There exists different types of classical and advanced Pulse Width Modulation (PWM) techniques to switch the traditional Voltage Source Inverter (VSI).The advanced PWM techniques are superior to classical PWM techniques in respect of load current ripple, Total Harmonic Distortions, switching losses. The same concept of advanced PWM techniques for VSI is applicable for Z-Source Inverter. This paper proposes certain vector sequences based on advanced PWM techniques for ZSI. The proposed vector sequences are analyzed in respect of load/line current ripple based on stator flux ripple concept. The superiority of the advanced PWM techniques over classical is verified by simulation study of a ZSI in PSim9.1.1 Environment for R-L and different motor load conditions.

A carrier-based, three-phase pulse-width modulation (PWM) technique for the control of motor drives that uses a stepped waveform as the reference signal is presented. The theoretical derivation of the stepped reference signal from a square-wave reference is described. Comparisons with existing sinewave PWM techniques, adopting third-harmonic boosting and regular sampling techniques, show that the square-wave PWM has a superior performance at low carrier frequencies. The adopted stepped reference waveform is shown to improve upon the square-wave strategy at high carrier frequencies. The practical realization of the PWM technique is described using performance criteria such as minimum pulse-widths, peak carrier frequencies, and the current harmonic distortion. >

Offline pulse width modulation (PWM) techniques are employed to reduce the line current distortion in induction motor (IM) drives where the switching frequency is highly constrained. An optimal PWM technique is proposed here for a neutral point clamped (NPC) inverter fed IM drive to minimize the motor current distortion, subject to constraints on number of switching instants per quarter cycle. Two types of pole voltage waveforms of the NPC inverter are considered, namely type-I and type-II. This paper reports optimal switching angles for both type-I and type-II waveforms to minimize the resulting total harmonic distortion (THD) in motor current. In general optimal type-II is found to result in lower THD than optimal type-I PWM. The optimal type-II PWM offers superior performance in terms of motor current distortion than synchronized sine-triangle PWM and selective harmonic elimination PWM, as shown by simulation and experimental results on an NPC inverter fed 3.7 kW induction motor drive.