SPARKSkein: A Formal and Fast Reference Implementation of Skein

Password managers (PMs) are important tools that enable the use of stronger passwords, freeing users from the cognitive burden of remembering them. Despite this, there are still many users who do not fully trust PMs. In this paper, we focus on a feature that most PMs offer that might impact the user’s trust, which is the process of generating a random password. We present three of the most commonly used algorithms and we propose a solution for a formally verified reference implementation of a password generation algorithm. We use EasyCrypt to specify and verify our reference implementation. In addition, we present a proof-of-concept prototype that extends Bitwarden to only generate compliant passwords, solving a frequent users’ frustration with PMs. This demonstrates that our formally verified component can be integrated into an existing (and widely used) PM.KeywordsPassword managerRandom password generatorFormal verificationSecurityEasyCryptJasminInteractive theorem provingVerified compilationBitwarden

Introduction. Widespread use of unmanned aerial vehicles in the civilian and military spheres requires the development of new algorithms for identification friend or foe of targets, as used in the Armed Forces of Ukraine (AFU) devices of the "Parol" system are designed to service approximately 110 objects military equipment. AFU automation systems allow the use of additional sources of information about various objects from civil or special data transmission networks, which can be the basis for building a networked multi-level system of state recognition. Predictions of the development of quantum computers foresee the possibility of breaking modern algorithms for information security in polynomial time in the next 5-10 years, which requires the development and implementation of new encryption algorithms and revision of modern parameters. The purpose of the article is to develop a new algorithm for state recognition of objects, which can be scaled to process the required number of manned and unmanned aerial vehicles. Potential threats to classical cryptographic protection algorithms for data networks, which will result in the execution of algorithms such as Grover and Shore on quantum computers, were also discussed. Results. The article proposes a new multilevel algorithm of state recognition based on modern cryptographic methods of information protection, which allows to perform reliable automated identification of objects, scale systems using data on potential targets from other sources through secure special networks. Grover's search algorithm does not give a strong increase in key search performance for symmetric encryption algorithms, so there is no need to increase the key lengths for this type of information security algorithms. Post-quantum asymmetric encryption algorithms require additional study and comprehensive testing of information security or increasing the key lengths of cryptographic algorithms, which corresponds to the number of qubits, i.e. more than twice. The most promising is the family of asymmetric post-quantum cryptographic algorithms based on supersingular isogenic elliptic curves. Conclusions. The developed algorithm of identification friend or foe of objects is more secure compared to existing algorithms and is focused on the use of modern on-board computers and programmable radio modems. Shore's algorithm and the like will be a significant threat to modern asymmetric cryptography algorithms when the number of qubits of quantum computers exceeds the number of bits in public keys more than twice. Keywords: identification friend or foe, symmetric encryption, asymmetric cryptography, quantum computer, post-quantum cryptography.

The Internet of Things (IoT) revolutionizes how we interact with smart devices. However, ensuring security in IoT systems presents complex challenges due to their centralized architecture and inherent limitations. The increasing attention towards blockchain technology stems from its decentralized structure, transparency, immutable records, and cryptographic hash functions, particularly when combined with the Internet of Things (IoT). Cryptographic hash algorithms are essential to blockchain technology, ensuring secure data transmission by linking private and public keys through mathematical functions. Existing cryptographic algorithms typically produce variable hash values accessible to a single node and support input key sizes up to 128 bytes. However, larger key sizes can reduce transaction accuracy, lower key entropy, decrease throughput, and increase transaction complexity. Conversely, smaller key sizes increase vulnerability to attacks. To overcome these challenges, several advancements have been proposed. A modified key signature scheme extends the key size to 256 bytes, achieving 82.6% accuracy, a time complexity of 1.68 nanoseconds, and a throughput of 15.24 kilobytes per 200 nanoseconds. However, this scheme operates on a single-node basis, limiting accessibility. These advancements aim to bolster security in IoT data transmission by integrating encryption techniques with blockchain technology. The performance of the modified signature scheme is analyzed through transaction parameters such as accuracy, time complexity, throughput, and hash output with cryptographic hash functions like SHA224, SHA256, SHA384, SHA512, MD5, SHA3-224, SHA3-256, SHA3-384, SHA3-512, and ECDSA. From this analysis, the elliptic curve cryptography algorithm gives higher accuracy and throughput with less time complexity.

This paper presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. MorphoSys, a dynamic reconfigurable architecture that sustains implementations that can yield into equally or even better performance results than custom-hardware and yet preserves all the flexibility of general-purpose processors. With today's great demand for secure communications systems, networks and the Internet, there is a growing demand for real-time implementation of cryptographic algorithms. As a case study, this paper presents the mapping and performance analysis for one of the five AES finalists cryptographic algorithms, namely RC6. Being an important and secure cryptographic algorithm, RC6 is considered well chosen to be mapped in order to test and evaluate the suitability of dynamic reconfigurable computer (RC) systems such as MorphoSys.

Due to the increasing attainability of quantum computers, the threat to traditional cryptographic algorithms is more relevant than ever before. However, the field of Post-Quantum Cryptography (PQC) to address this is still young and may potentially exhibit security vulnerabilities. In this paper, the role of Pre-Shared Keys (PSK) is analyzed in an attack scenario with both traditional and post-quantum algorithms potentially broken. We present a scheme for improved integration of external PSKs into a PQC-secured TLS 1.3 handshake, with a focus on no security compromises and broad deployment options. In that context, the protection of long-term secrets on dedicated security tokens and the integration of Quantum Key Distribution (QKD) are elaborated. For QKD integration, our scheme enables a deployment without QKD-specific changes to TLS. In addition to the scheme itself, a reference implementation is presented and evaluated to demonstrate its technical viability. Our results indicate that the general integration of PSKs into the TLS handshake adds negligible overhead while substantially increasing the achieved security level. Although deployments using dedicated security tokens or QKD systems have a significant influence on handshake times, specific applications could benefit greatly from the added security guarantees.

Objectives: The implementation of Genetic algorithm in the symmetric block cipher Advanced Encryption Standard -128 (AES-128) algorithms to enhance the performance of cryptographic operations. Methods: Genetic algorithm is used for generating the best fit non-repetitive cipher key and for key distribution to design a dynamic Substitution box in AES-128. Findings: The study reveals that the efficiency of the cryptographic algorithm treated with Genetic algorithm is dependent on the variations in the number of generations and initial population size. The result shows that an optimum population size has less encryption and decryption time. Among the sample population size taken for the experiment, almost the average population size has minimum encryption and decryption time. Results from iteration variations shows that the average number of iterations has less encryption and decryption time. Improvements: The hybrid combination of Genetic algorithm and AES-128 can be further modified for images and audio messages also. Keywords: Genetic Algorithm, Iterations, Non-Repetitive Cipher Key, Population Size, Substitution Box

Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, various schemes to protect cryptographic devices against such attacks have been devised and some implemented in practice. Almost all of these protection schemes target an individual side-channel attack and consequently, it is not obvious whether a scheme for protecting the device against one type of side- channel attacks may make the device more vulnerable to another type of side-channel attacks. We examine in this paper the possibility of such a negative impact for the case where fault detection circuitry is added to a device (to protect it against fault injection attacks) and analyze the resistance of the modified device to power attacks. To simplify the analysis we focus on only one component in the cryptographic device (namely, the S-box in the AES and Kasumi ciphers), and perform power attacks on the original implementation and on a modified implementation with an added parity check circuit. Our results show that the presence of the parity check circuitry has a negative impact on the resistance of the device to power analysis attacks.

Developing a general component system for a statically typed, object-oriented language is a challenging design problem for two reasons. First, mutually recursive references across components are common in object-oriented programs-an issue that has proven troublesome in the context of component systems for functional and procedural languages. Second, inheritance across component boundaries can cause accidental method overrides. Our recent research shows that a component framework can be constructed for a nominally typed object-oriented language supporting first-class generic types simply by adding appropriate annotations, syntactic sugar, and component-level type-checking. The fundamental semantic building blocks for constructing, type-checking and manipulating components are provided by the underlying first-class generic type system. To demonstrate the simplicity and utility of this approach we have designed and implemented an extension of Java called Component NEXTGEN (CGEN). CGEN, which is based on the Sun Java 5.0 javac compiler, is backwards compatible with existing Java binary code and runs on current Java Virtual Machines. The primary contribution of this paper is a technical analysis of the subtle design issues involved in building a component framework for a nominally typed object-oriented language supporting first-class generics. In contrast to component systems for structurally typed languages, mutual recursion among components is accommodated in the type system and semantics without incorporating any special machinery. Our analysis includes a presentation of Core CGEN (CCG), a small, core language modeling the CGEN framework. It is based on Featherweight GJ and incorporates some ideas from MIXGEN. CCG adds the essential features to support components, but nothing more. Our discussion includes the type rules and semantics for CCG, as well as a proof of type safety.

Focusing is a proof-search strategy, originating in linear logic, that elegantly eliminates inessential nondeterminism, with one byproduct being a correspondence between focusing proofs and programs with explicit evaluation order. Higher-order abstract syntax (HOAS) is a technique for representing higher-order programming language constructs (e.g., λ's) by higher-order terms at the"meta-level", thereby avoiding some of the bureaucratic headaches of first-order representations (e.g., capture-avoiding substitution).

Abstract: Cryptographic application plays an important role in wireless communication, especially, a FPGA built-in RFID tag on UHF band (860-960 MHz). The information safety can be obtained by applying suitable and advanced cryptographic algorithm. This paper simulates the installation and implementation of cryptographic algorithm on a FPGA using Isim software from Xilinx. The result shows that the implementation of 128-bit Advanced Encryption Standard-AES improved considerably the operating speed by 565000 ps for both encryption and decryption process. Similarly, the 233-bit multitive algorithm kP on elliptic curve also enhanced then operating speed at 467661900000 ps. Using above mentioned algorithm, the system maintains the security level meanwhile it does not require very high hardware configuration.

The design flow of a digital cryptographic device must take into account the evaluation of its security against attacks based on side channels observation. The adoption of high level countermeasures, as well as the verification of the feasibility of new attacks, presently require the execution of time-consuming physical measurements on the prototype product or the simulation at a low abstraction level. Starting from these assumptions, we developed an exploration approach centered on high level simulation, in order to evaluate the actual implementation of a cryptographic algorithm, being it software or hardware based. The simulation is performed within a unified tool based on SystemC, that can model a software implementation running on a microprocessor-based architecture or a dedicated hardware implementation as well as mixed software-hardware implementations with cycle-accurate resolution. Here we describe the tool and provide a large set of design explorations and characterizations based on actual implementations of the AES cryptographic algorithm, demonstrating how the execution of a large set of experiments allowed by the fast simulation engine can lead to important improvements in the knowledge and the identification of the weaknesses in cryptographic algorithm implementations.

The RFID technology in combination with cryptographic algorithms and protocols is discussed widely as a promising solution against product counterfeiting. Usually the discussion is focussed on passive low-cost RFID-tags, which have harsh power constraints. 4-Bit microcontrollers have very low-power characteristics (5-60 muA) and are therefore an interesting platform for active and passive low-cost RFID-tags. To the best of our knowledge there are no implementations of cryptographic algorithms on a 4-bit microcontroller published so far. Therefore, the main contribution of this work is to demonstrate that cryptography is feasible on these ultra-constrained devices and to close this gap. We chose PRESENT as the cryptographic algorithm, because contrary to many other ciphers, PRESENT uses a 4times4 S-Box. Our implementation draws a current of 6:7 muA at a supply voltage of 1:8 V and a frequency of 500 KHz and requires less than 200 ms for the processing of one data block.

Side-channel analysis (SCA) is launched by exploiting the information leaking from the implementation a cryptographic algorithm, e.g., power consumption information. Recently, deep learning-based SCA techniques have also facilitated SCA against software and hardware implementations of various cryptographic algorithms. In this work, we perform SCA using various deep learning (DL) techniques such as Multi-layered Perceptron (MLP), Convolutional Neural Network (CNN), and Recurrent Neural Network (RNN) on the datasets collected from hardware and software platforms. The objective of this work is to identify the performance of DL techniques in performing SCA for secret key recovery and finding out the best settings for the model to optimize the attack performance in terms of on computation time and SCA efficiency. In our study, we have focused on two open-source AES-128 encryption algorithm databases, ASCAD and DPA contest v2 (DPAv2), where ASCAD database consists of the power traces captured from a software implementation of the AES and DPAv2 database consists of the power traces captured a hardware implementation of the AES. For the first time, we applied hyperparameter tuning with Bayesian Optimization and distributed computing on ASCAD database and we investigated the impact of MLP and RNN along with the distributed computing and hyperparameter tuning with Bayesian optimization on DPAv2 database. Our results show that the CNNs are the best models for performing the attack on software implementation while MLPs are the best for attacking hardware implementation of cryptographic algorithms.

Implementations of cryptographic algorithms continue to proliferate in consumer products due to the increasing demand for secure transmission of confidential information. Although the current standard cryptographic algorithms proved to withstand exhaustive attacks, their hardware and software implementations have exhibited vulnerabilities to side channel attacks, e.g., power analysis and fault injection attacks. This paper focuses on fault injection attacks that have been shown to require inexpensive equipment and a short amount of time. The paper provides a comprehensive description of these attacks on cryptographic devices and the countermeasures that have been developed against them. After a brief review of the widely used cryptographic algorithms, we classify the currently known fault injection attacks into low-cost ones (which a single attacker with a modest budget can mount) and high-cost ones (requiring highly skilled attackers with a large budget). We then list the attacks that have been developed for the important and commonly used ciphers and indicate which ones have been successfully used in practice. The known countermeasures against the previously described fault injection attacks are then presented, including intrusion detection and fault detection. We conclude the survey with a discussion on the interaction between fault injection attacks (and the corresponding countermeasures) and power analysis attacks.

An offline E-cash system is presented that offers appreciably greater security and better privacy than currently considered E-cash system with similar functionality. Most off-line E-cash systems use the temper-resistant IC card which controls an E-cash issued by the card issuer. Offline E-cash system based on IC card has the threats of overspending, double spending, forgery E-cash, altering/eavesdropping transaction contents, etc. To prevent the above threats, there have been a lot of technical discussions of the security requirements for theoretical offline E-cash protocols based on IC card. However, there has been little attention paid to the security requirements for practical offline E-cash system based on IC card including entity authentication, key management, implementation of cryptographic algorithm, etc. Thus, this paper describes the security requirements for cryptographic algorithms, integrity for implementation of cryptographic algorithm, authentication module, key management, and E-cash protocols