Specification, modeling and design tools for system-on-chip

In this paper, we describe FLEXBUS, a flexible, high-performance on-chip communication architecture featuring a dynamically configurable topology. FLEXBUS is designed to detect run-time variations in communication traffic characteristics, and efficiently adapt the topology of the communication architecture, both at the system-level, through dynamic bridge by-pass, as well as at the component-level, using component re-mapping. We describe the FLEXBUS architecture in detail and present techniques for its run-time configuration based on the characteristics of the on-chip communication traffic. The techniques underlying FLEXBUS can be used in the context of a variety of on-chip communication architectures. In particular, we demonstrate its application to AMBA AHB, a popular commercial on-chip bus. Detailed experiments conducted on the FLEXBUS architecture using a commercial design flow, and its application to an IEEE 802.11 MAC processor design, demonstrate that it can provide significant performance gains as compared to conventional architectures (up to 31.5% in our experiments), with negligible hardware overhead.

As application complexity continues to increase, multiprocessor systems-on-chip (MPSoC) with tens to hundreds of processing cores are becoming the norm. While computational cores have become faster with each successive technology generation, communication between them has become a bottleneck that limits overall chip performance. On-chip optical interconnects can overcome this bottleneck by replacing electrical wires with optical waveguides. In this paper we propose an optical ring bus (ORB) based on-chip communication architecture for next generation MPSoCs. ORB uses an optical ring waveguide to replace global pipelined electrical interconnects while preserving the interface with today's bus protocol standards such as AMBA AXI. We present experiments to show how ORB has the potential to provide superior performance (more than 2times) and significantly lower power consumption (a reduction of more than 10times) compared to traditionally used pipelined, all-electrical bus-based communication architectures, for 65-22 nm technology nodes.

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.The techniques underlying Flexbus are general, and are applicable to a variety of bus standards. We have implemented Flexbus as an extension of the popular AMBA AHB bus, and have evaluated it using a commercial design flow. We report on experiments conducted to analyze its area, timing, and performance under a wide variety of system-level traffic profiles. We have applied Flexbus to two example SoC designs: 1) an IEEE 802.11 MAC processor and 2) an UMTS turbo decoder. Our results show that Flexbus provides gains of up to 34.55 % in application data-rates over conventional architectures, with negligible area overhead and a 3.2% penalty in clock period.

The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper we present a framework to generate a dynamically reconfigurable crossbar-based on-chip communication architecture that can support multiple use-case bandwidth and latency constraints. Our framework generates on-chip communication architectures with a low cost, low power dissipation, and with minimal reconfiguration overhead. Results of applying our framework on several networking CMP applications show that our approach is able to generate a crossbar solution with significantly lower cost (2.4× to 3.8×), and lower power dissipation (1.5× to 3.1×), compared to the best previously proposed approach.

With technology improvements, the main bottleneck in single chip systems in terms of performance, power consumption, and design reuse is proving to be generated by the on-chip communication architecture. Therefore, packet oriented on-chip interconnection schemes have been proposed as an alternative to traditional bus-based structures, which are inherently non scalable. However, such interconnection architectures have to be during the very early stages of the design flow. The objective of this work is to present an application independent stochastic framework for high level performance analysis of networks-on-chip based communication architectures. Such a template allows the designer the performance evaluation of various competing on-chip communication architectures early in the design flow.

With technology improvements, the main bottleneck in terms of performance, power consumption, and design reuse in single chip systems is proving to be generated by the on-chip communication architecture. Benefiting from the non-uniformity of the workload in various signal processing applications, several dynamic power management policies can be envisaged. Nevertheless, the integration of on-line power, performance and information-flow management strategies based on traffic monitoring in (dynamically) reconfigurable templates has yet to be explicitly tackled. The main objective of this work is to define the concept of run-time functional optimization of application specific standard products, and show the importance of integrating such techniques in reconfigurable platforms and especially their communication architectures.KeywordsInterconnection NetworkCommunication ArchitectureDynamic Power ManagementDesign ReusePower Management PolicyThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

This paper presents a method of on-chip commaunication topology synthesis for a shared multi-bus based architecture. An assumption for the synthesis is that the system has already been partitioned and mapped onto the appropriate components of a SoC so that size of data to be transferred at each time by an on-chip module is fixed. We model the communication behavior of each module as a set of communication lifetime intervals (CLTIs), which are optimized in terms of number of overlaps among them, size of bus width and the minimum number of buses, using ILP (integer linear programming) formulation. These optimized CLTIs are later given to the communication topology synthesis algorithm, which gives the number of buses and their interconnection. The results of applying this approach to the Talking Assistant used in ubiquitous computing application demonstrate the utility of our techniques to synthesize a custom on-chip shared multibus based communication architecture for a complex system.

In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern systems-on-a-chip (SOC). Their techniques are based on the following observations: 1) Conventional test compression schemes, which are designed to satisfy various constraints including low hardware overheads and decompression times, cannot fully exploit compression opportunities present in test data and 2) due to the diversity of components used in SOCs (and consequently in their test strategies and test-data characteristics), a single compression strategy may not be best suited to handle them. The authors propose the use of multilevel and heterogeneous test compression schemes to address the above issues and demonstrate that they can provide significant reductions in the test volume above currently known state-of-the-art test compression techniques. An architecture that reuses infrastructure components already present in SOCs (programmable processors, on-chip communication architecture, memory, etc.) for an efficient implementation of their techniques is proposed. Finally, the authors suggest various architectural-customization techniques, such as partitioning of the decompression functionality between the hardware and software and the addition of custom instructions, to improve decompression times and reduce hardware overheads. Experiments with several designs, including an industrial media-processing SOC, demonstrate the efficacy of the proposed techniques in achieving test-data-volume reductions with low overheads

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.

Soc is a technology that integrates heterogeneous system components such as microprocessors, memory logic and DSP's into a single chip. The overall performance of SoC design depends on efficient on-chip communication architectures. Efficient interconnection architecture is necessary interprocessor communication, communication between processors and peripherals and between processor and memory. The communication architecture should be flexible in such a way that it should adapt to various traffic conditions. Currently on-chip interconnection networks are mostly implemented using shared buses which are the most common medium. The arbitration plays a crucial role in determining performance of bus-based system, as it assigns priorities, with which processor is granted the access to the shared communication resources. In the conventional arbitration algorithms there are some drawbacks such as bus starvation problem and low system performance. Hence in this paper, probability based dynamically configurable Round robin arbiters are proposed to handle the discrepancy of existing arbitration algorithms. This bus provides each component a flexible and utmost share of on-chip communication bandwidth and improves the latency in access of the shared bus. The performance of SoC is improved using this probabilistic round robin algorithm with regard to the parameters, latency compared to conventional bus arbitration algorithms.

In order to achieve functionality with low energy speed product, on-chip parallel and network-based system design requires larger device, multi block functions, and energy evaluation schemes. Such systems,which are emerging as the architecture of choice for future high performance processors, require efficient interconnect which are necessary to satisfy the data supply needs of all cores. This special issue attempts to cover new ideas in the design and analysis of on-chip communication technology, architecture, design methods and applications. In what follows, we will give a brief overview of the accepted papers of this Special Issue based on their topics.

Interconnects have been shown to be a dominant source of energy consumption in modern day System-on-Chip (SoC) designs. With a large (and growing) number of electronic systems being designed with battery considerations in mind, minimizing the energy consumed in on-chip interconnects becomes crucial. Further, the use of nanometer technologies is making it increasingly important to consider reliability issues during the design of SoC communication architectures. Continued supply voltage scaling has led to decreased noise margins, making interconnects more susceptible to noise sources such as crosstalk, power supply noise, radiation induced defects, etc. The resulting transient faults cause the interconnect to behave as an unreliable transport medium for data signals. Therefore, fault tolerant communication mechanisms, such as Automatic Repeat Request (ARQ), Forward Error Correction (FEC), etc., which have been widely used in the networking community, are likely to percolate to the SoC domain.This paper presents a survey of techniques for energy efficient on-chip communication. Techniques operating at different levels of the communication design hierarchy are described, including circuit-level techniques, such as low voltage signaling, architecture-level techniques, such as communication architecture selection and bus isolation, system-level techniques, such as communication based power management and dynamic voltage scaling for interconnects, and network-level techniques, such as error resilient encoding for packetized on-chip communication. Emerging technologies, such as Code Division Multiple Access (CDMA) based buses, and wireless interconnects are also surveyed.

This paper presents Lotterybus, a novel high-performance communication architecture for system-on-chip (SoC) designs. The Lotterybus architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of Lotterybus: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the Lotterybus architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4\% reduction in communication latencies over conventional on-chip communication architectures).

The object of the study is the Network-on-Chip (NoC) technology, which has become a popular choice for the on-chip communication architecture of modern System-on-Chip (SoC) devices. The subject matter of the article is methods of reducing dissipated power in NoC and SoC. The goal of the work is: development of a low-power coding method that allows for the efficient transmission or storage of information. The following tasks are solved in the article: analysis of classification methods for combinatorial structures, construction a system of typical representatives and analysis of their characteristics. The research methods are based on the use of set theory, system theory and combinatorics. The following results are obtained: analyzed factors that affect the dissipated power, considered principles of constructing energy-efficient codes. It is shown that switching activity significantly affects the total power and one of the effective methods for reducing switching activity during communication between devices or on-chip communication is the use of low-power coding methods. A method of hierarchical classification of unit distance codes and algorithms for solving step-by-step problems have been developed. The method is based on the invariant approach and construction of a system of different representatives. Estimates of their number have been obtained, characteristics have been determined, and catalogs of typical representatives have been formed. Conclusions. The article analyzes factors that affect dissipated power, and considers the principles of constructing energy-efficient codes. A method of hierarchical classification of single distance codes and algorithms for solving step-by-step problems have been developed, and catalogs of typical representatives have been formed. The application of the developed method will allow developers to analyze and select codes with the best properties and, as a result, obtain better results in terms of network delays, energy costs, and other design limitations for computer systems.

The contemporary networks-on-chip (NoCs) are becoming a viable on-chip communication architecture to serve the demand of high-performance requirements of multicore platforms. Mesh-based NoCs (MoCs) that provide efficient, interconnected infrastructures are popularly accepted as the scalable medium to the requirements. However, the MoCs fall short of meeting the stringent system requirements while the network size increases and resulting in the issue of long-distance communications. This paper presents altering a traditional MoC to corresponding Hybrid architecture that addresses the problem and provides improved performance. The proposed scheme transforms an MoC with a few wireless routers to handle the long-distance communication in MoCs. Evaluation of the proposed method on a 32-bit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> Hybrid MoC shows that the network achieves latency as of 30167.897 cycles, network throughput of 12.8824 flits/cycle, and energy consumption as of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$29.9182\ \mu\mathbf{J}$</tex> , respectively. Compared to the traditional <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times 8$</tex> MoC, the proposed Hybrid architecture improves packet loss, latency, and throughput metrics up to 96%, 98.36%, and 25.77%, respectively. This achievement is about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$8\times$</tex> faster than many existing approaches.