Squeegee Influence on Bump Metrics for Stencil Printed Wafers

PurposeSolder paste printing is the most common method for attaching surface mount devices to printed circuit boards (PCB), and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as land grid array (LGA) and quad-flat no-lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The aim of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations.Design/methodology/approachStencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using solder paste inspection system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated thermal cycling (ATC) was used to determine the reliability of the solder joints. Failure analysis was used to determine if the failure was attributed to the low paste volume locations.FindingsSolder joints formed with nominal paste volume survived longer in ATC compared to intentionally low volume joints. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA and QFN devices. A lower volume limit is reported for leadless devices that should not significantly affect yield and reliability in thermal cycling.Originality/valueVery little literature is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50 or ±30 per cent of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints.

As the trend toward further miniaturisation of pocket and handheld consumer electronic products continues apace, the requirements for even smaller solder joints will continue. With further reductions in the size of solder joints, the reliability of solder joints will become more and more critical to the long-term performance of electronic products. Solder joints play an important role in electronics packaging, serving both as electrical interconnections between the components and the board, and as mechanical support for components. With world-wide legislation for the removal/reduction of lead and other hazardous materials from electrical and electronic products, the electronics manufacturing industry has been faced with an urgent search for new lead-free solder alloy systems and other solder alternatives. In order to achieve high volume, low cost production, the stencil printing process and subsequent wafer bumping of solder paste has become indispensable. There is wide agreement in industry that the paste printing process accounts for the majority of assembly defects, and most defects originate from poor understanding of the effect of printing process parameters on printing performance. The printing of ICAs and lead-free solder pastes through the very small stencil apertures required for flip chip applications was expected to result in increased stencil clogging and incomplete transfer of paste to the printed circuit pads. Paste release from the stencil apertures is dependent on the interaction between the solder paste, surface pad and aperture wall; including its shape. At these very narrow aperture sizes the paste rheology becomes crucial for consistent paste withdrawal because for smaller paste volumes surface tension effects become dominant over viscous flow. Successful aperture filling and release will greatly depend on the rheology of the paste material. Wall-slip plays an important role in characterising the flow behaviour of solder paste materials. The wall- slip arises due to the various attractive and repulsive forces acting between the solder particles and the walls of the measuring geometry. These interactions could lead to the presence of a thin solvent layer adjacent to the wall, which gives rise to slippage. The wall slip effect can play an important role in ensuring successful paste release after the printing process. The aim of this study was to investigate the influence of the paste microstructure on slip formation for the paste materials (lead-free solder paste and isotropic conductive adhesives). The effect of surface roughness on the paste viscosity was investigated. It was also found that altering the surface roughness of the parallel plate measuring geometry did not significantly eliminate wall slip as was expected. But results indicate that the use of a relatively rough surface helps to increase paste adhesion to the plates, inducing structural breakdown of the paste. Most importantly, the study also demonstrated on how the wall slip formation in the paste material could be utilised for understanding of the paste microstructure and its flow behaviour

There is a great deal of interest in solder paste printing in flip chip assembly. The advantages of this process are low cost and high throughput. However, to meet this challenge there is a need to evaluate the stencil printing process parameters. These parameters can be divided into printer parameters, stencil parameters, environmental parameters, and solder paste parameters. The parameters evaluated in this paper are the stencil and solder paste parameters. Several different stencils with various shapes, sizes and pitches were investigated; these dimensions determine the type of solder paste that can be printed. In this paper, we address the need for new paste formulation characterisation, and present a procedure for evaluating solder pastes developed for flip chip application via the stencil printing process. Rheological measurements are used to correlate solder paste behaviour to stencil printing process performance. Fundamental procedures used in industry for characterisation in shear conditions include rheograms (flow curves), thixotropic index and single point viscosity measurements. We show how viscosity changes can be quantified. Viscosity measurements were carried out on a controlled stress-strain Reologica StressTech rheometer with parallel plate geometry. We also report on solder paste creep/recovery properties and how they can be correlated to slump. To correlate solder paste rheological properties to stencil printing behaviour, several printing tests were carried out. These tests can help define the process window for any given flip chip application, in terms of limiting pitch size, pad size and minimum pad gap.

This brand new course begins with the basics of SMT solder paste stencil printing and ends with the latest research in stencil printing tools and technologies. The class starts with a quick description of printing fundamentals: solder paste characteristics and behaviors, the mechanics of the process and importance of a good setup, and the relationship between aperture sizes and paste deposit formations. It then progresses rapidly into troubleshooting techniques for both general and specific printing issues, and addresses problem prevention through proper stencil design and selection. Moving into advanced technology topics, the course reviews the last four years of independent research on stencil materials, manufacturing processes and nanocoatings, and closes with an update of automated Solder Paste Inspection (SPI) technologies, applications and special features. Attendees are encouraged to ask questions or bring specific problems to the class for suggestions and inputs. Topics Covered: Solder paste Mechanics of the printing process Troubleshooting process problems Stencil design Stencil materials and manufacturing processes Automatic Solder Paste Inspection (SPI) Review and Q&A Who should attend: SMT assembly process engineers and technicians responsible for production or new product introductions processes Engineers and technicians just entering the SMT field who want to quickly learn the science and art of stencil printing SMT quality personnel interested in helping improve print and end-of-line yields OEM supplier quality engineers responsible for supporting and/or assessing SMT assembly contractors. Instructor Bio: Chrys Shea is the President of Shea Engineering Services, a consulting firm that produces technical studies and communications tools for the electronics manufacturing industry. With several hundred publications to her credit, Chrys leverages her 20+ years of process engineering and management experience to create documents, presentations, web pages and other items that deliver complex technical topics clearly and effectively. Chrys is a favorite speaker at SMTA events, and has twice received the SMTAI Best of Conference award for her work on solder paste printing. In 2012 she was honored with the SMTA Member of Technical Distinction award. Chrys earned her B.S. in Mechanical Engineering from the University of Massachusetts and her M.S. in Manufacturing Engineering from the University of Rhode Island, and is a past president of the Philadelphia SMTA Chapter. She launched Shea Engineering services in 2008. On Demand Webinar

The assembly of Printed Circuit Boards (PCBs) consists of several processes and sub-processes. Literature and experience suggests that solder paste deposition during stencil printing is the primary cause of defects [3]. Therefore, an organization must encompass robust processes such that the occurrence of defects is prevented. Process control entails understanding the manufacturing process and its variation along with the variation of the measurement systems employed. Automated solder paste inspection with 100% board and component coverage is relatively new to the Surface Mount Technology (SMT) industry. This paper addresses the approach to quantify variation in the measurement system. A scientific and systematic methodology to analyze a 3-D automated solder paste inspection system based on Measurement System Analysis (MSA) studies is delineated. As part of the MSA study, standard approaches have been developed for conducting accuracy analyses, linearity studies, and Gage Repeatability and Reproducibility (GR&R) analyses for automated solder paste inspection equipment. The approach suggested is validated by case studies on two sets of automated solder paste inspection equipment. Results of the case study are discussed.

This paper presents recent work on solder paste printing for wafer-level bumping at sub 100mum pitch using Pb-free solder paste with IPC type-6 (15-5mum) particle size distributions. Consistent sized paste deposits have been produced onto wafers at such a pitch using stencil printing. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have on the reproducibility of the deposits. With the reduction of pitch and aperture size, large volumes of paste are required during reflowing of the fine particle solder paste to allow sufficient stand-off between the flip chip device and substrate. This volume of pastes affects also the print consistency and uniformity of the bumps generated. Printing defects from a large number of printing trials have been examined statistically for several bump geometries. The best print parameters were then used to print paste deposits onto wafers containing bond pads for reflow. Stencil printing process at ultra fine pitch demands refinements to both solder paste design and stencil manufacturing technology. Advancements in stencil fabrication methods have produced 'state-of-the-art' stencils exhibiting highly defined shaped apertures with smooth walls at ultra fine pitch, thus allowing for improved solder paste release at very small pitch and aperture size dimensions. The engineering of the paste rheology in terms of shear thinning, tackiness and visco-elastic properties was carried out by varying the metal content and flux type. The design of new paste material has also be conducted alongside a design of experiments to adjust printing parameters such as printing speed, pressure, print gap and separation speed to allow for a practical process window

Modelling the effect of uneven PWB surface on stencil bending during stencil printing process

The stencil printing process in electronics production asks for permanent optimization because of its sensitivity to process defects like solder paste bridges, insufficient or even missing solder paste. The performance of the stencil technology within the printing process contributes significantly to the productivity and the quality of this important and complex process. The paper presents the new and innovative technology of nano-coated stencils. This includes the coating process and the coating material as well as the resulting stencil characteristics and the potentials of the nano-coated stencil for the printing process. The nano-coating is an innovative finishing technology to improve the stencil performance. The production takes place by a so called sol-gel process, a unique process with an economical possibility to realize a permanent and functional coating on the stencil surface. The nano-coating that covers the aperture walls and the stencil bottom side provides a hydrophobic characteristic with the consequence of a reduced adhesion between stencil surface and solder paste. The potentials of nano-coated stencils are illustrated on the basis of extensive printing experiments. On the one hand nano-coated stencils show less paste residues on the stencil bottom side with the consequence of significantly decreased stencil cleaning intervals. This leads to higher line efficiency and a reduced consumption of cleaning material. On the other hand the improved release behavior results in higher transfer efficiencies, especially for apertures with a critical area ratio. With regard to the stencil design, the area ratio of nano-coated stencils can be reduced down to a value of approximately 0.4. Both effects of nano-coated stencils contribute to a very robust and economical printing process.

Stencil printing for flip chip packaging using fine particle solder pastes is a low cost assembly solution with high throughput for fine pitch solder joint interconnects. The manufacturing challenges associated with both solder paste printing increases as electronic device size decreases due to trend of miniaturization in electronic components. Among multiple parameters, the two most important stencil printing parameters are squeegee pressure and printing speed. In this paper, the printing behavior of Pb free Sn-3Ag-0.5Cu solder paste with a particle size distribution of 2–12 μm for wafer level bumping using a stencil printing method (stencil opening dimension −30 μm) was evaluated by varying the printing speed and squeegee pressure to fabricate solder bumps with a sub 100 μm size. The optimal squeegee pressure and print speed for the defect free printing behavior and fairly uniform size distribution of reflowed paste were found to be 7 kgf and 20 mm/s, respectively. The average size of the reflowed printed paste decreased with the increasing squeegee pressure.

As the July 1, 2006 Pb-free deadline approaches, many electronics assemblers are beginning to fathom the changes and process demands required. The two biggest material concerns involve solder paste and components. This document provides practical recommendations for evaluating Pb-free solder pastes and ensuring that the selected solder paste will deliver assembly yields comparable to, or better than, the incumbent Sn/Pb solder paste. Since it is commonly considered that a Pb-free process is more difficult to control (due to more constraints on the printing and reflow), the use of statistics becomes even more essential in the evaluation of solder pastes. Without proper statistical techniques, it is difficult to accurately assess and rank the performance of various solder paste candidates. Statistics allow the user to adequately characterize variation. There is variation in every process, but operational efficiencies decrease as the variation from the target result increases. Statistics reveal the differentiation between common cause variation, which is controllable and expected, and special cause variation, which is unnatural and not expected. The special cause variation is what typically would result in a defect in the SMT process. When considering a Pb-free solder paste evaluation, there are a couple of things that need to be defined to enable statistical analysis: Define the part of the process to be evaluated: The smaller and less complicated that the evaluation is, the easier it is to characterize and measure results. It is better to run several small experiments than try one large experiment that tries to characterize a large number of variables. An example would be to evaluate the print performance of the various Pb-free solder pastes. Define the factors to evaluate: In the stencil printing process, one factor is the different Pb-free solder pastes. Other factors include various print speeds, the length of time between prints (response to downtime), etc. Define the response variables: It is essential to know the product attributes that are of the greatest importance to the process. These are the variables that should be measured. In the stencil printing example, solder paste volume is most often studied and is considered the most crucial variable. Once the experimentation results are collected, the statistical analysis begins. When comparing Pb-free solder pastes, the best paste is the one that provides the process the greatest precision (most consistent results) as well as greatest accuracy (results closest to the targeted values) i .

In today's high-pressure environment, electronics manufacturers are expected to deliver higher flexibility, lower costs, and greater product reliability, often simultaneously. This system is answering that call with a disruptive approach to surface-mount technology (SMT) production. Built on a proprietary LIFT (Laser-Induced Forward Transfer) platform, it replaces traditional stencil and jet printing with a fully digital, contactless, high-precision solder paste deposition system, ushering in a new standard for efficiency and accuracy, in a system which is developed and built in Europe. Despite enormous advances in component miniaturization, circuit board assembly continues to rely on stencil printing technology from the 1980s for the initial, and most error prone, step of PCBA production. This somewhat outdated process is responsible for up to 70% of production line defects, especially in high quality, high-mix, low-to-medium volume environments where it is harder to optimize processes. As a result, manufacturers face daily challenges including line downtime, costly rework, and inconsistent quality. This LIFT based platform addresses these legacy issues head-on. By using an ultra-high-resolution laser to transfer precise volumes of solder paste from a donor glass plate directly onto the PCB pads, at very high speed, the system delivers much improved volumetric control with no satellites or contact. Supporting and tested on a huge range of standard Type 4 and Type 5 solder pastes, the solution avoids the high costs associated with specialized pastes and significantly simplifies supply chain logistics. A core innovation is Integrated Solder Paste Volume Metrology (SPVM) . Unlike traditional SPI systems, which rely on image-based analysis, SPVM captures real volumetric measurements in real time. This enables in-process control with unprecedented precision, leading to higher first-pass yields, full traceability, and a more robust quality framework. The digital nature of the platform brings several operational advantages: programming can be completed in under 15 minutes using Gerber or ODB++ files, reducing setup times by up to 90%. Moreover, by eliminating the need for other machines, stencils and alignment tooling, capital investments for capacity scaling can be reduced by over 60%. From a sustainability perspective, the solution cuts energy usage, and generates minimal waste. These environmental benefits, combined with the system's software-driven control, make it highly appealing to the next-generation workforce and align with modern ESG targets, (Environmental, Social and Governance). This revolutionary new system can dramatically improve process reliability, boost EBIT, and meet the ever more challenging demands of high-performance electronics production. As many countries look to reindustrialize and strengthen their strategic independence, particularly in sectors like aerospace and defense, this system offers more than just a process improvement. It delivers a transformative step toward smarter, cleaner, added flexibility and more competitive electronics manufacturing.

For some years now, an area ratio of 0.66 or greater has been the criterion for stencil apertures to achieve acceptable volume control in the printed solder paste “brick,” for small apertures Meeting this criterion, in the stencil printing process, has been a constant concern as the volume consistency of the solder paste brick is among the most critical metrics in determining high yields in the assembly process. With the advent of 0201 and most recently 01005 passives components, meeting the area ratio target of 0.66 is a challenging task; especially with a 5 mil thick stencil and a Type 3 powder solder paste. These tiny passive technologies and minimalist IC packages like 0.4mm CSPs have created a need to re-evaluate the area ratio criterion of 0.66 and other related issues. In light of this need, we developed a series of designed experiments (DOEs) evaluating Type 3 and Type 4 solder pastes, varying aperture designs for 0201, 01005 and 0.4 mm CSPs, and 3 and 4 mil thick laser cut and E-Fab stencils. In these experiments we determined optimum print parameters for the various combinations of pastes, components, aperture design, and stencil fabrication mentioned above. Our results also suggested new criteria for area ratios. We believe that with the concurrent implementation of leadfree assembly, this work could not be more timely.

The continual miniaturization of electronics components for personal electronics devices, coupled with the conversion to RoHS- and REACH-compliant lead-free assemblies, has put a tremendous strain on the electronics assembly industry. Introduction of 01005 passives, and active components on the order of 0.3mm pitch, initiates newly defined questions about specification limits for solder paste stencil print performance. This paper discusses variability of solder paste print performance and its relationship to specification limits. The objective is to describe analyses to determine stencil print process character, using actual paste print measurement data. Aside from setting specification limits, application of statistical methods for the analysis of variation in stencil print performance could help understand appropriate production statistical process control (SPC) limits sought by SMT manufacturing and quality engineers from stencil print inspection results that are gathered during SMT assembly. Effects on values of Cp and Cpk by various specification limits are presented. This discussion is based on recent application development experiments, to elucidate how average solder paste measurement and standard deviation measurement effect new print process capability challenges. From this work, a strategy to optimize a new 01005 stencil printing process is reviewed. Importantly, the discussion includes key factors with planning quality aspects of SMT assembly. SPC techniques presented will show how to measure stencil print performance capability, and result in opportunity for reduced assembly costs and increased sales income.

The increasing demand for portable electronics continues to be a dominant factor for technological advancements in the development of fine pitch devices. Assembling these highly compact and high Input/Output (I/O) density devices efficiently on Printed Circuit Board (PCB) assemblies can be a challenging task. Extensive literature is available focusing on stencil printing challenges and reliability studies of fine pitch devices. However, for 0.40 mm pitch Ball Grid Array (BGA) components, the effect of key factors like pad design of the PCB (Solder Mask Defined – SMD and Non-Solder Mask Defined - NSMD), solder paste type, and stencil technology on the stencil printing process requires further research. Also, the solder paste print definition for fine pitch printing greatly depends on the capabilities of the stencil printer and on printing process parameters. In this paper, the effect of PCB pad design (SMD/NSMD), and solder paste type (Type 3/Type 4) have been studied and discussed. Additionally, the performances of three different stencil printers were studied to determine their effect on the solder paste volume and print definition. Automated Solder Paste Inspection (SPI) was used to measure the print quality in terms of print volume, print height as well as printing defects such as solder bridging. Based on the results, the volume of solder paste deposited was higher in the case of NSMD pads as compared to SMD pads. Both type 3 and type 4 solder pastes were found to be compatible for the assembly of a 0.40 mm pitch BGA. It was also observed that the printing process and print quality were more dependent on the stencil printer used in the case of the 0.40 mm pitch components as compared to coarser pitch components, such as 0.50 or 0.80 mm pitch devices.

Tin-Bismuth (SnBi) solder alloys are being explored in the consumer electronics industry due to the benefit of low reflow temperatures when compared to Tin-Silver-Copper (SAC solders). These benefits include cost savings due to lower reflow temperatures in reflow ovens, reduction of temperature-driven component warpage, and elimination of the high-temperature material costs for components and printed circuit boards (PCB) to survive a SAC reflow process. An additional benefit of the SnBi’s low reflow temperature is the potential for eliminating the selective or wave soldering process and associated operating costs and factory space by soldering through-hole components with a Pin-in-Paste (PiP) process. The cost of a wave soldering tool can exceed $300,000 and switching to the PiP process can help eliminate this expense along with savings associated with tool maintenance, raw materials, and headcount. PiP uses a Surface Mount Technology (SMT) process to print solder paste at and around the Through Hole Mount (THM) location. Leads of the THM part can then be placed or inserted in the paste deposit either by an automated machine or manually. Paste forms a solder joint with the leads and via when the boards are sent through the reflow oven. Thus, this process can be combined with routine SMT parts and improve the throughput. Many papers have successfully demonstrated SAC PiP through hole soldering. However, the SAC PiP process has not gained traction due to the increased material costs for through-hole components that can survive SAC reflow temperatures which can be between 230ºC-250ºC. LTS solder paste reduces reflow temperatures to below 190ºC which makes it feasible for components with a lower temperature rating to be soldered during SMT reflow via Pin in Paste process. A drawback of the PiP process is that it can be difficult to achieve sufficient and uniform barrel fill as it involves the use of a stencil to print the necessary paste volume on the board. Stencil printing has an inherent limitation on the amount of paste volume it can deposit due to restrictions on the X, Y, and Z dimensions of the stencil aperture. This limitation is not observed at the wave and selective as they provide a continuous flow of solder paste to the PTH component to meet the higher paste volumes needed to fill the PTH barrel. This paper addresses various methods to overcome the limitations of the PiP process by defining the formula needed to calculate necessary solder paste volume. It recommends a ratio for the barrel to lead diameter, a comparison between the effect of board thickness on barrel fill percentage, and a proposal to use 100% lead coverage criteria for boards thicker than 62 mils. A lead pull test was performed on the 2x4 headers built with 100% lead coverage solder joint quality (SJQ) criteria using SnBi PiP process to study its solder joint strength and co-relate solder joint quality between the PiP and the Wave process. The test results were inconclusive in comparing SJQ between PiP and Wave as the pull test fixture failed to hold on to the header after 1kg of pulling force due to slippage.