START: System Testability Analysis and Research Tool

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult, mainly due to the problem of justifying test sequences at the inputs of a core embedded deep in the circuit and propagating test responses from the core outputs. In this paper, we first present a design for testability technique for testing such core-based systems. In this scheme, untestable cores are first made testable using hierarchical testability analysis techniques. If necessary, additional testability hardware is added to the cores to make them transparent so that they can propagate test data without information loss. This testability and transparency technique is currently applicable to cores of the following types: application-specific integrated circuits, application-specific programmable processors, and application-specific instruction processors. Other core types can be made testable and transparent using traditional techniques. The testable and transparent cores can then he integrated together with some system-level testability hardware to ensure justification of precomputed test sequences of each core from system primary inputs to the core inputs and propagation of test responses from core outputs to system primary outputs. Justification and propagation of test sequences are done at the system level by extending and suitably modifying the symbolic hierarchical testability analysis method that has been successfully applied to register-transfer level circuits. Since the testability analysis method is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a byproduct of the testability analysis and insertion method without further search. The test methodology was applied to six example systems. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated: (1) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan and (2) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

Due to the complexity of test generation for stuck-at-faults in synchronous sequential circuits and the permanently increasing problem-size, algorithms solving this problem cannot work with acceptable CPU-time, even on computer systems with very high performance. Relating to this context this paper presents a new testability analysis guiding algorithms for sequential test generation. This testability analysis consists of two separated parts: First, a new technique for the detection of untestable stuck-at-faults; second, heuristics used to guide the decision process in test generation algorithms. Experimental results of sequential benchmark circuits allow us to conclude that our testability analysis provides less CPU-time for sequential test generation than other well-known testability analysis tools. >

To ensure proper implementation, the DFT process has to be supported by a comprehensive set of tools for system specification, design verification, testability analysis, test generation and software validation. Any DFT/DFD strategy has to be based on a thorough understanding of the cost of test structure over the life of the automotive products. Without a viable cost of test model it will be impossible to justify the test features added to the module that usually impact the cost of design and are of benefit only for the later stages ofthe product life

Background: HIV drug resistance (HIVDR) threatens progress achieved in response to the HIV epidemic. Understanding the costs of implementing HIVDR testing programs for patient management and surveillance in resource-limited settings is critical in optimizing resource allocation. Here, we estimate the unit cost of HIVDR testing and identify major cost drivers while documenting challenges and lessons learnt in implementation of HIVDR testing at a tertiary level hospital in Kenya. Methods: We employed a mixed costing approach to estimate the costs associated with performing a HIVDR test from the provider's perspective. Data collection involved a time and motion study of laboratory procedures and interviewing laboratory personnel and the management personnel. Cost analysis was based on estimated 1000 HIVDR tests per year. Data entry and analysis were done using Microsoft Excel and costs converted to US dollars (2019). Results: The estimated unit cost for a HIVDR test was $271.78 per test. The main cost drivers included capital ($102.42, 37.68%) and reagents (101.50, 37.35%). Other costs included: personnel ($46.81, 17.22%), utilities ($14.69, 5.41%), equipment maintenance costs ($2.37, 0.87%) and quality assurance program ($4, 1.47%). Costs in relation to specific laboratory processes were as follows: sample collection ($2.41, 0.89%), RNA extraction ($22.79, 8.38%), amplification ($56.14, 20.66%), gel electrophoresis ($10.34, 3.80%), sequencing ($160.94, 59.22%), and sequence analysis ($19.16, 7.05%). A user-initiated modification of halving reagent volumes for some laboratory processes (amplification and sequencing) reduced the unit cost for a HIVDR test to $233.81 (13.97%) reduction. Conclusions: Capital expenditure and reagents remain the most expensive components of HIVDR testing. This cost is bound to change as the sequencing platform is utilized towards maximum capacity or leveraged for use with other tests. Cost saving in offering HIVDR testing services is also possible through reagent volume reduction without compromising on the quality of test results.

In this paper, we consider imperfect test sequencing problem under a single fault assumption. Our approach is based on the comparing the imperfect test phenomenon to perfect test, and the integrating this phenomenon into the test sequencing strategy, called IPT-TS strategy. The results of numerical simulations on the test case show that the proposed approach significantly decreases test costs and is more adaptable to solve test sequencing problems with imperfect test for diagnosis when compared with that based on the random strategy.

In this paper, we propose a new testability analysis method for Register-Transfer Level (RTL) descriptions. The proposed method is based on the idea of testability analysis in terms of data-flow and control structure which can be extracted from RTL designs. We analyze testability of RTL descriptions with more testability measures than those of conventional gate-level testability, so that the method provides information for design for testability (DFT). We have implemented the presented method and experimental results show that we can reduce circuit cost for test and achieve highly testable circuits by DFT using our RTL testability analysis.

A novel test optimizing algorithm for sequential fault diagnosis

In a fundamental paradigm shift in system design, entire systems are being built on a single chip, using multiple embedded cores. Though the newest system design methodology has several advantages in terms of time-to-market and system cost, testing such core-based systems is difficult due to the problem of justifying test sequences at the inputs of a core embedded deep in the system, and propagating test responses from the core outputs. In this paper, we present a design for testability and symbolic test generation technique for testing such core-based systems on a chip. The proposed method consists of two parts: (i) core-level DFT to make each core testable and transparent, the latter needed to propagate test data through the cores, and (ii) system-level DFT and test generation to ensure the justification and propagation of the precomputed test sequences and test responses of the core. Since the hierarchical testability analysis technique used to tackle the above problem is symbolic, the system test generation method is independent of the bit-width of the cores. The system-level test set is obtained as a by-product of the testability analysis and insertion method without further search. Besides the proposed test method, the two methods that are currently used in the industry were also evaluated on two example systems: (i) FScan-BScan, where each core is full-scanned, and system test is performed using boundary scan, and (ii) FScan-TBus, where each core is full-scanned, and system test is performed using a test bus. The experiments show that the proposed scheme has significantly lower area overhead, delay overhead, and test application time compared to FScan-BScan and FScan-TBus, without any compromise in the system fault coverage.

The test sequencing problem is optimized to reduce test cost and ensure the performance of Fault detection and diagnosis (FDD), which is the intersection of FDD and Design for Testability (DFT). Considering the false and missing alarm of complex system diagnosis, this paper proposed an optimal test sequence strategy for fault diagnosis under unreliable test based on the quasi-depth first search (QDFS) algorithm. Firstly, the method established a heuristic evaluation function considering fault diagnosis abilities, information entropy, test cost and the reliability of the test. Then, the quasi-depth first search algorithm is used to build the fault diagnosis strategy. The theory and experiments demonstrate that the cost based on the QDFS method is much better than greed algorithm. Therefore, the proposed method could be used to design the strategy for fault diagnosis under unreliable test.

ABSTRACTThe use of multiple tests can improve medical decision making by balancing the benefits of correctly treating ill patients and avoiding unnecessary treatment for healthy individuals against the potential harms of missed diagnoses, inappropriate treatments, and the costs and risks associated with testing. We quantify the incremental net benefit (INB) of single and multiple tests by accounting for a patient's pre‐test probability of disease and the associated benefits, harms, and cost of treatment and testing. We decompose the INB into two components: one that captures the value of information provided by the test, independent of the cost and possible harm of testing, and another that accounts for test costs and harm. Next, we examine conjunctive, disjunctive, and majority aggregation functions, demonstrating their application through examples in prostate cancer, colorectal cancer, and stable coronary artery disease diagnostics. Our approach complements traditional threshold and decision‐curve analysis by varying both the pre‐test probability of disease and the cost‐benefit trade‐off of treatment to identify the region over which a given test provides the highest INB. Using empirical test and cost data, we compute decision boundaries to determine when conjunctive, disjunctive, majority, or even single tests are optimal, and, for combinations of tests, in what order they should be administered. In all three application examples, we find that the optimal choice and sequence of tests jointly depend on the probability of disease and the cost‐benefit trade‐off of treatment. An online tool that visualizes the INB for combined tests is available at https://optimal‐testing.streamlit.app/.

Test sequencing problem arising at the design stage for reducing life cycle cost

With advancements in manufacturing and design technology, memory integration density has improved. However, as integration density increases, the cost of testing and repairing memory has also risen, posing a significant challenge in memory production. To address this challenge, built-in self-repair (BISR) has been proposed. Traditional built-in redundancy analysis (BIRAs) performs limited analysis of faults during the fault collection process, resulting in a significant delay in generating a repair solution after the test sequence is completed. This inefficiency arises from the time required to repair the memory posttest. This article proposes a new fast and optimal BIRA using smart potential case collection. The proposed BIRA conducts a detailed analysis of detected faults during the test process. Using this novel fault collection results, a potential case is generated. This is a repair case that can repair the memory with a high probability and is generated immediately after the test sequence ends. If the memory cannot be repaired by the potential case, an exhaustive search is conducted for the faults requiring further analysis to generate an optimal repair solution. Compared to previous studies, the proposed BIRA demonstrates extremely low analysis time with an optimal repair rate.

Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence. We propose a new diagnosis approach for short faults in interconnects. The pin-adjacency fault model is assumed. By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults. Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence. This can significantly save the diagnosis cost for boundary-scan testing. An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets. The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line. If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In Israel, below-grade culverts are critical structure as they are essential points of the water transport network across the country. A lack of maintenance may create safety hazards and economic loss. The current maintenance strategy is that of breakdown maintenance. Such strategy has the drawback of high repair and maintenance costs. This study presents a methodology to determine the optimal maintenance strategy for below-grade culverts during their design life, by evaluating life cycle performances and life cycle costs. A field survey aimed at collecting critical data to develop a suitable deterioration pattern model. An exponential model was found to be the most significant statistically. A Markov chain model was implemented to determine the culvert life cycle performances and life cycle costs. A Maintenance Effectiveness Indicator (MEI) determines the best life cycle maintenance strategy among: breakdown, performance-based, and preventive maintenance. The best maintenance strategy was found to be the preventive. It provides with the highest cost effectiveness and allows for knowing the required budget in advance. Preventive maintenance strategy, which is strongly associated with Lean Construction, permits to save 80% of the resources required under the breakdown maintenance regime. The methodology can be extended to other assets of the roadway infrastructure.

Applications of deep learning to electronic design automation (EDA) have recently begun to emerge, although they have mainly been limited to processing of regular structured data such as images. However, many EDA problems require processing irregular structures, and it can be non-trivial to manually extract important features in such cases. In this paper, a high performance graph convolutional network (GCN) model is proposed for the purpose of processing irregular graph representations of logic circuits. A GCN classifier is firstly trained to predict observation point candidates in a netlist. The GCN classifier is then used as part of an iterative process to propose observation point insertion based on the classification results. Experimental results show the proposed GCN model has superior accuracy to classical machine learning models on difficult-to-observation nodes prediction. Compared with commercial testability analysis tools, the proposed observation point insertion flow achieves similar fault coverage with an 11% reduction in observation points and a 6% reduction in test pattern count.