Static power model for CMOS and FPGA circuits

Starting from deep submicron technologies (< 0.13μm), and even stronger in nanometer technologies, static power consumption, due to leaky “off” transistors, is becoming a non-negligible contributor to the total power dissipation. Under this condition, the total power optimization problem changes considerably. The high parallelization approach commonly used today to increase performances, will soon result in power ineffcient designs. Indeed, the static power consumption of the large number of rarely used transistors will highly penalize the total power consumption. The purpose of this thesis is to investigate the influence of static power on the design methodologies for low power. In particular, the effects of architectural as well as technology modifications are explored. The use of technology as an optimization parameter has become possible in recent technologies. In fact, they offer different threshold voltages, each one showing a different trade-off between speed and leakage current. In this work, two different frameworks are considered. In the first one, both the supply voltage and the transistor threshold voltage are freely tunable parameters. This is the most general case and corresponds to the situation where the designer has the largest freedom. In the latter framework, we assume that the designer cannot change the supply voltage nor the transistor threshold voltage and they are hence considered constants. This case corresponds to the most common one, where the designer has a supply voltage and a technology type (and hence a threshold voltage) fixed by the application and by the devices the circuit has to interface. In both cases, lot of efforts have been put to the development of a handy way to rapidly estimate the total power consumption and consequently easily compare different architectural/technology variants at the early stages of development. Examples, based on multipliers, are used extensively in the whole thesis and, at the end, the presented theory is applied to a real circuit implemented in a 90nm technology by ST Microelectronics. Measurements show a very large variability of the static power over 16 dies manufactured on the same wafer. For instance, the highest static power consumption at nominal condition (Vdd=1V, f=62.5MHz) over the lowest one corresponds to more than a factor of 2.5. Measured data also report multipliers able to work at 210mV for a frequency of 1MHz!

In todaypsilas technology generations, e.g. 90 and 65 nm, the static power consumption becomes a major contributor to the total power consumption. It is therefore important to consider all abstraction levels to reduce this power. This paper focuses on the arithmetic level and shows a methodology for a substantial reduction of the static power consumption. Both the dynamic and static power consumption is evaluated for bit-parallel and bit-serial arithmetic. Simulations are done in a typical 130 nm technology. With only a minor cost in dynamic power consumption, a static power reduction up to 13 times is shown by using bit-serial arithmetic.

Portable electronic devices are integral components in our quotidian life. These devices require charging after a certain amount of usage time. Most of the time during discharging cycle, they remain idle or inactive. If these devices are not in active use, why does the battery discharge? The answer is leakage power consumption. At present the power density in CMOS integrated circuits has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. With downward scaling of technology, static power consumption is becoming more dominant. It is challenging for the circuit designers to balance both scaling and low static power demands. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using stacked sleep transistor without being penalized in power delay product requirement and circuit performance.

Kernel-based template attacks of cryptographic circuits using static power

Flex Power FPGA can flexibly control the operating speed and power consumption by flexible assignment of the threshold voltage to transistor. This paper evaluates the static power consumption and area overhead on various threshold voltage control granularity in the Flex Power FPGA based on specific settings. There is the trade-off relationship between static power and area overhead in threshold voltage control granularity in Flex Power FPGA with bulk MOS transistors. Moreover, division of the threshold voltage controlled transistor area has a big influence on the trade-off. For example of evaluation results, static power reduces less than 1/5 of original level, while increase an area overhead of less than 40% by appropriately dividing the threshold voltage controlled transistor areas. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained.

Personal portable devices such as DMB (digital multimedia broadcasting)s, PMP (portable multimedia player)s and PDA (portable digital assistant)s require long battery life without reducing their performance. Power consumption is one of important factors in ubiquitous environments. To reduce the dynamic power consumption, many researches have been conducted on the dynamic voltage and frequency scaling (DVFS). DVFS can reduce the power consumption proportionally to the square of the supply voltage. But processor operation under the critical speed increases the leakage current. Larger leakage current increases the static power consumption. This paper proposes a new power-aware scheduling algorithm that reduces the static and dynamic power consumption to use frequency scaling between two discrete voltage levels and under the critical speed while meeting the deadline of given applications. The simulation and experimental implementation show that the proposed scheduling algorithm results in up to 25% energy gains over traditional DVFS algorithms with two task scheduling policies.

As increasing concern for environmental sustainability urges to bring attention to green-aware multi-agent systems, we put forward a game-theoretic model in which agents compete for the usage of power-consuming resources and are charged a cost proportional to their fair share of the power consumption. Using the widely adopted cube-root rule for CMOS-based devices, our model becomes a congestion game in which two distinct parts coexist, namely, congestion games with polynomial latency functions and fair cost-sharing games. The interplay between these two components is governed by two resource-specific constants regulating the static and dynamic power consumption of each resource. Our findings show that, despite these games being highly inefficient in the general case (a super-constant price of stability), performance at equilibrium significantly improves (a constant price of anarchy) when the ratio between the static and dynamic power consumption of each resource remains bounded by a constant. This suggests that, in uncoordinated green-aware multi-agent systems, technology plays a fundamental role in shaping the efficiency of stable solutions.

Due to scaling, many limitation arise for CMOS-based design memory cells in the nanometre regime, i.e. it becomes necessary to find a substitute for this design. Low power and high speed integrated circuits (ICs) are the demand of the electronics industry in many applications such as Internet of things (IoT) and electronics gadgets, e.g. Mobile, Laptops etc. Now, modern design ICs uses carbon nanotube FET or FinFET to design memory cells because of their excellent features of having low leakage and delay and improved performance. In this paper, two 10 transistor (10 T) FinFET design SRAM cells are proposed along with their hold, read, and write static noise margins (HSNM, RSNM, and WSNM), dynamic and static power consumption. These cells consume low power and provide high stability for electronic gadgets. In the proposed cells, we used a separate read and write path and back gate control method (BG). A comparative analysis of the proposed cells is done with the existing 10 T CMOS and FinFET based cells. All cells are simulated by using the tool HSPICE at 32 nm technology for a supply of 0.5 V. Cells 1 and 2 dissipate 69% and 85% less static power, 54% and 68% less read power and 17% and 56% less write power, respectively, compared to the 10 T FinFET cell. Results signify that the proposed independent gate (IG) FinFET based cells have the highest value of margins and the least value power consumption.

Latest nanometer CMOS technology nodes have highlighted new issues in security of cryptographic hardware implementations. The constant growth of the static power consumption has led to a new class of side-channel attacks. Common attacks exploiting static power use an univariate approach to recover information from cryptographic engines. In our work, a multivariate approach based on information theoretic security metrics is presented. The temperature-dependence helps to exploit more information leakage from the hardware implementation. Starting from a univariate analysis, mutual information reveals that increasing the working temperature, the information leaked through the static power side channel is increased as well. In this work a multivariate analysis exploiting static power consumption is presented in which the temperature-domain is used to extract more information. The use of information theoretic approach allows to precisely quantify the amount of information that can be leaked from a cryptographic hardware implementation. The perceived information shows taking advantage of the use of more than one temperature, the security level can be decreased. The improvement achieved using the presented approach is demonstrated on a 40 nm CMOS implementation of the Present 80 crypto core.

The scaling of microelectronic technologies brings new challenges to the design of complex SoCs. For example, fully synchronous SoCs may soon become unfeasible to build. Asynchronous design techniques increasingly mingle within SoC design procedures to achieve functional and efficient systems, where synchronous modules are independently designed and verified. This is followed by module integration by means of asynchronous interfaces and communication architectures, forming a globally asynchronous, locally synchronous (GALS) system. Among multiple asynchronous design styles, the quasi delay insensitive (QDI) stands out for its robustness to delay variations. When coupled to delay insensitive (DI) codes like m-of-n and to four-phase handshake protocols, the QDI style produces the dominant asynchronous template currently in use. This work presents a technique to reduce the static power consumption of asynchronous QDI circuits using any m-of-n code and a four-phase handshake protocol, by proposing the utilization of a non-classical spacer encoding, namely all-1s. The article shows that the use of the traditional all-0s spacers may lead to static power consumption figures that are in some cases more than twice larger than the static power consumed by all-1s spacers in C-elements, the most common device used in asynchronous templates. Experiments demonstrate the new spacer reduces static power consumption without increase in complexity.

Static power due to leakage current will become a major source of power consumption in the nanometer technology era. In this paper, we propose a simple yet effective technique to reduce both static and dynamic power consumption in the scan test process. The leakage current is restrained by selecting a good primary input vector to control the paths of leakage current during the scan shift process, and this vector can also be used to reduce dynamic power. However, the reverse is not always true. A heuristic algorithm is presented to find such vectors. The proposed method is simulated by SPICE with BPTM 22nm transistor model, and the results show that on the average 15% total power reduction is achievable by the proposed method.

An ultra-low power regulator system for WSNs powered by energy harvesting

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ±60 µA, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ±1V from ±1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 µV/√Hz, and the maximum linearity error is 4.1%.

This paper presented the analysis of total power dissipation of AP-DCD algorithm using field programmable gate arrays (FPGAs). The static and dynamic power dissipation investigated using leakage current, supply voltage, effective capacitance and toggling frequency of the AP-DCD algorithm. It was found that the effective capacitance of AP-DCD algorithm was the main factor for the dynamic power dissipation and leakage current was the main factor for the static power dissipation. The total power dissipation was calculated by the addition of static and dynamic power. From the simulated calculation we found that the consumption of the dynamic power (2.1 mW) was significantly less than the static power (219.75 mW) dissipation and the total power consumption was 221.85 mW. Xilinx-Virtex-II Pro XC2VP30 device is one of the commonly used programmable fabrics, which was employed here for all the calculation.

A fully power aware globally asynchronous locally synchronous network-on-chip circuit is presented in this paper. The circuit is arranged around an asynchronous network-on-chip providing a 17 Gbits/s throughput and automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each NoC units. The dynamic power consumption can be reduced up to a factor of 8 while the static power consumption is reduced by 2 decades in stand-by mode.