Statistical sampling of microarchitecture simulation

This paper proposes a parallel cycle-accurate microarchitectural simulator which efficiently executes its workload by splitting the simulation process along time-axis into many intervals. This time-division parallelization is similar to the concept of trace-splitting parallelization but is completely different from this conventional technique because our simulator assures that its result is perfectly equivalent to what a sequential simulator produces. The assurance of the perfect accuracy is endued by a simple failure recovery mechanism; if i-th interval is simulated by a node with an approximate initial machine state which causes invalid result, the interval is simulated again by the node responsible to (i - 1)-th interval and thus having the correct state at the beginning of i-th interval. In order to reduce the possibility of the interval failure for efficiency, the fully cycle-accurate simulation for an interval is preceded by a partial and thus fast micro architectural simulation including that for caches, branch predictors and their interaction in speculative execution. Another important technique is to check the validity of an interval simulation by comparing approximate and correct initial states with respect to their effect to the subsequent execution, rather than the raw values of them. The effectiveness of these techniques are exhibited by our SimpleScalar-based implementation and its evaluation with SPEC CPU95 benchmarks which results that 8-node and 16-node parallel simulations achieve up to 5.8-fold and 9.4-fold speedup respectively

Performance simulation of software for Multiprocessor System-on-a-Chips (MPSoC) suffers from poor tool support. Cycle accurate simulation at Instruction Set Simulation level is too slow and inefficient for any design of realistic size. Behavioral simulation, though useful for functional analysis at high level, does not provide any performance information that is crucial for design and analysis of MPSoC implementations. As a consequence, designers are often reduced to manually annotate performance information onto behavioral models, which contributes further to inefficiency and inaccuracy. In this paper, we use structural performance models to provide fast and accurate simulation of software for MPSoC. We generate structural models automatically using GCC with accurate performance annotation while considering optimizations for instruction selection, branch prediction, and pipeline interlock. Our structural models are able to simulate at several orders of magnitude faster than ISS and provide less than 1% error on performance estimation. These models allow realistic MPSoC design space explorations based on performance characteristics with simulation speed comparable to behavioral simulation. We validate our simulation models with several benchmarks and demonstrate our approach with a design case study of an MPEG-2 decoder.

Laboratory pulse-decay techniques are effective for determining rock permeabilities ranging from 0.01 μd to 0.1 md. However, the measurement time is fairly long, reaching up to several hours to days when testing gas shales because their permeability can be as low as dozens of nano-Darcys. This paper proposes an alternative pulse-decay technique that offers accurate permeability measurements within a considerably short time frame. A radial-flow pulse decay method with a new experimental design is developed, which employs two gas reservoirs of the same volume and two pressure pulses with the same magnitude, one "positive" and one "negative". A mathematical model is then developed to numerically verify the feasibility of the newly developed technique and analytically solved for permeability estimation. Pressure responses with time in the radial direction of the test sample are analyzed and compared with those in the axial direction by solving the mathematical model. A concentric circular cavity with a diameter of 0.51 cm is created along the core samples, which are tested to experimentally demonstrate the applicability of the technique. The numerical results showed that the pressure pulse of the radial flow decays much faster than the axial flow and at least a 10-fold reduction in measurement time can be achieved. Numerical results indicated that the proposed technique is capable of eliminating the effects of the compressive storage and gas sorption in the permeability measurement; while great efforts need to be put to correct such effects when employing conventional transient techniques. An in-depth comparison is experimentally made between the proposed method and the conventional axial-flow method. The experimental results presented in the study confirm that fast and accurate measurements can be achieved using the proposed technique.

Digital levels deliver highly accurate and fast measurements in an automated measuring process. A shortcoming is that they give less accurate measurements in some cases. There are several sources which are known to have a systematic effect on the height reading and therefore have to be investigated for our equipment. One parameter is the scale factor which has to be determined on a regular basis. Other sources for inaccurate height readings are measurements at critical distances and at the end sections of the rod, a defocused set-up and artificial illumination. With the findings of the experiments investigating the aforementioned error sources, rules for our fieldwork were established. The experiments were carried out with our instruments, a Trimble (formerly Zeiss) DiNi 12 (SW Version 1.21) and a Leica DNA03 (SW Version 3.40). In some cases, when it is not possible to avoid a critical set-up with the digital leveling system, we use the analog level Wild NA3. Therefore the analog rods have to be also controlled. The calibration is performed with a CCD camera which automatically detects the edges in the image and compares them with the interferometer readings. The CCD camera system is also used to determine the height offset between rods.

In this paper we develop a framework for fast and accurate multiprocessor system performance simulation. Our simulation model generator generates simulation modules with accurate time deltas for software processes based on the intermediate representations generated by a compiler. The simulation modules are simulated as concurrent tasks in multiprocessor system performance simulation environment in SystemC. We use aggregated waits to reduce overhead in the simulation kernel and triple the speed of the simulation. Our study shows that we can obtain overall system performance results with less than 6% error while simulating at 150times faster than using an Instruction Set Simulator. This opens up system design space explorations that were not possible before.

This paper presents the VIPRO-MP (Virtual Prototype for Multiprocessor Architectures), an environment for virtual prototype development and simulation. The VIPRO-MP is constructed in SystemC, easing the specification of multiple processors prototypes and the inclusion of hardware IP components. The processors are based on the SimpleScalar superscalar processor simulator, providing the configuration of each core in terms of caches, branch predictor and internal processor features. This flexibility enables the VIPRO-MP to be used in the evaluation and tunning of embedded platforms where an optimized design in terms of performance and power consumption is needed. A JPEG encoding algorithm was used as case study to evaluate different platforms in terms of processors number and cache size, providing a fast performance and power consumption estimation.

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture (EA) to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters (instruction set, branch predictor, data path, memory hierarchy, concurrency, status & control, and so on) on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP (energy-delay product) for 31.14 % in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals’ lengths and their elasticities.

rSesame is a generic modeling and simulation framework which can explore and evaluate reconfigurable systems at the early design stages. The framework can be used to explore different HW/SW partitionings, task mappings and scheduling strategies at both design time and runtime. The framework strives for a high degree of flexibility, ease of use, fast performance and applicability. In this paper, we want to evaluate the framework's characteristics by showing that it can easily and quickly model, simulate and compare a wide range of runtime mapping heuristics from various domains. A case study with a Motion-JPEG (MJPEG) application demonstrates that the presented model can be efficiently used to model and simulate a wide variety of mapping heuristics as well as to perform runtime exploration of various non-functional design parameters such as execution time, number of reconfigurations, area usage, etc.

Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditional code placement techniques have less benefit in the presence of a trace cache that alters the placement of instructions in the instruction cache. Moreover, as pipelines have become deeper to accommodate increasing clock rates, branch misprediction penalties have become a significant impediment to performance. We evaluate pattern history table partitioning, a feedback directed code placement technique that explicitly places conditional branches so that they are less likely to interfere destructively with one another in branch prediction tables. On SPEC CPU benchmarks running on an Intel Pentium 4, branch mispredictions are reduced by up to 22% and 3.5% on average. This reduction yields a speedup of up to 16.0% and 4.5% on average. By contrast, branch alignment, a previous code placement technique, yields only up to a 4.7% speedup and less than 1% on average.

Building framework for selecting finite element models of complex large welded structure of railway vehicles

Performance of modern day computer systems greatly depends on the wide range of workloads, which run on the systems. Thus, a representative set of workloads, representing the different classes of real-world applications, need to be used by computer designers and researchers for processor design-space evaluation studies. While a number of different benchmark suites are available, a few common benchmark suites like the SPEC CPU2006 benchmarks are widely used by researchers either due to ease of setup, or simulation time constraints etc. However, as the popular benchmarks such as SPEC CPU2006 benchmarks do not capture the characteristics of the wide variety of emerging real-world applications, using them as the basis for performance evaluation may lead to either suboptimal designs or misleading results. In this paper, we characterize the behavior of the data analytics workloads, an important class of emerging applications, and perform a systematic similarity analysis with the popular SPEC CPU2006 & SPECjbb2013 benchmarks suites. To characterize the workloads, we use hardware performance counter based measurements and a variety of extracted micro-architecture independent workload characteristics. Then, we use statistical data analysis techniques, namely principal component analysis and clustering techniques, to analyze the similarity/dissimilarity among these different classes of applications. In this paper, we demonstrate the inherent differences between the characteristics of the different classes of applications and how to arrive at meaningful subsets of benchmarks, which will help in faster and more accurate targeted early hardware system performance evaluation.

A novel sampling technique for accurate and fast speed measurement is presented. Square pulses from an encoder are turned into ramps using analog electronics. They are then sampled, and linear regression is used on ramp-waveform sample points to extrapolate backward and determine the starting point of each pulse very accurately.

An accurate and fast fiber transfer delay measurement method is demonstrated. As a key technique, a simple ambiguity resolving process based on phase discrimination and frequency measurement is used to overcome the contradiction between measurement accuracy and system complexity. The system achieves a high measurement accuracy of 0.2 ps with a 0.1 ps measurement resolution and a large dynamic range up to 50 km as well as no dead zone.

Increasing concrete market and growing variety of concrete products and requirements for higher quality needs fast and accurate moisture measurement technology. In this paper fast accurate and material independent moisture measurement method is presented. Time domain reflectometry (TDR) sampling method for data acquisition has been used. In order to find the relationship between materials type and spectrum curve artificial neural network classifier (ANN) has been used. 5 mixtures from two materials (sand and crashed stone) in different proportions were correctly recognized using method proposed. Experiment confirmed ability to use TDR combined with ANN in material independent moisture measurement systems. Ill. 15, bibl. 9 (in English; summaries in English, Russian and Lithuanian).

Three-dimensional (3D) shape measurement of fringe projection profilometry (FPP) with high speed and accuracy is required in many applications. The measurement speed of FPP system is mainly limited by the low frame rate of pattern projection. Although defocusing binary patterns can be used to increase the measurement speed greatly, it will decrease the measurement depth. To this end, a novel triangular pattern generation method is proposed in this paper. By designing and projecting binary strip patterns with focused projector, images of triangular patterns can be then acquired with high frame rate. Fast and accurate 3D shape measurement can be finally obtained by using phase-shifting triangular patterns. Compared with the traditional sinusoidal patterns, the proposed method can improve the projection rate more than 4 times. Moreover, the proposed method will not decrease the measurement depth. Experimental results are given to confirm the validity of the proposed method.