Stress Analysis for Chip Scale Packages with Embedded Active Devices under Thermal Cycling

This paper describes a novel wafer level package using a silicone under the bump (SUB) design. The SUB architecture is designed to access the elastomeric qualities of silicones to reduce stresses on solder joints in a chip scale package. Poor reliability of the solder joints frequently arises from stresses generated by the mismatch in coefficient of thermal expansion between the die and the printed circuit board (PCB). Integration of a low modulus silicone pad between the die and solder ball allows for additional deformation mechanisms to dissipate stress between the die and the PCB during thermal cycling, increasing device reliability. Key to the realization of a SUB device was the integration of an elastomeric pad using the recently commercialized Dow Corning/sup /spl reg// WL-5150 photodefinable spin-on silicone. SUB devices containing 40 /spl mu/m thick silicone pads were successfully built using a series of standard processing steps including photolithography, plasma cleaning, and metallization. Two different SUB solder joint designs, suggested by FEA, were constructed and evaluated under thermal cycling. Failure mechanisms in the devices were determined to be dependent on the metallization scheme for the electronic connections. Incorporation of the silicone pads in a SUB device resulted in a 90% increase in reliability relative to control devices without the silicone pad. The failure mechanisms observed suggested an intermediate metallization approach to further enhance reliability.

In this work, a systematic study was performed in order to evaluate the influences of chip scale package (CSP) materials on the reliability of the soldered joints. The type of adhesive interconnecting the top and bottom layers of silicon was varied in this study. The materials alternatives evaluated comprise a hard epoxy material with high filler content, a rubber-like adhesive and an adhesive in medium state. These were combined with the substrate materials, FR4 and Al/sub 2/O/sub 3/, on which the CSPs are mounted. A unified viscoplastic constitutive model was applied to represent the temperature and time dependent deformation behaviour of the solder material. The stress/strain responses of CSP solder joints under thermal cycling conditions were evaluated using the finite element method. From the results, solder joint lifetimes were estimated with a crack propagation model. The results show that under thermal cycling conditions, the CSP solder joint lifetimes are lower when the CSP is fabricated with a highly filled adhesive compared to those with a rubber-like adhesive. Also, the solder joint reliability of CSPs mounted on FR4 substrates is inferior to those on Al/sub 2/O/sub 3/ substrates. This is due to the fact that the internal adhesive layer in a CSP also serves as the source of thermal expansion mismatch. Furthermore, a more flexible CSP design can reduce stresses in the soldered joints. Some discussions for material selection of epoxy adhesive in CSP are also presented. Consequently, a structural adhesive with a low elastic modulus and low CTE is more desirable than a harder material.

Finite element modeling is widely used for estimating the solder joint reliability of electronic packages. In this study, the electronic package is a CSP mounted on a printed circuit board (PCB) using an area array of solder joints varying from 5×4 up to 7×7. An empirical model for estimating the reliability of CSP solder joints is derived by correlating the simulated strains to thermal cycling results for 20 different sample configurations. This empirical model translates the inelastic strains calculated by nonlinear three-dimensional (3D) finite element simulations into a reliability estimation (N50% or N100 ppm). By comparing with the results of reliability tests, it can be concluded that this model is accurate and consistent for analyzing the effect of solder joint geometry. Afterwards, parameter sensitivity analysis was conducted by integrating a design of experiment (DOE) analysis with the reliable solder fatigue prediction models, following the method of simulation-based optimization. Several parameters are analyzed: the PCB parameters (elastic modulus, coefficient of thermal expansion, thickness), the chip dimensions (area array configuration), and the parameters defining the solder joint geometry (substrate and chip pad diameter, solder volume). The first study analyzes how the solder joint geometry influences the CSP reliability. A second study is a tolerance analysis for six parameters. These parameters can have a tolerance (=accuracy) of their nominal value, and it is shown that these small tolerances can have a significant influence on the solder joint reliability.

With the great environmental concern, lead-free solders gradually replace lead-based solders in electronic packages. However, the relatively short history of lead-free solders makes their reliability database inadequate. In other words, there is an urgent need to establish the reliability information of lead-free solders. In this study, a failure analysis is conducted to investigate the reliability of lead free solders. The test vehicle is the flip chip on board (FCOB) with the size of 8 mm*8 mm*0.29 mm, 0.5 mm pitch and an I/O array of 16times16 balls. The device is chosen for its recent popularity in the semiconductor packaging industry. The device includes the silicon chip, solder balls, polymeric underfill and substrate. The analysis is performed by a 3D finite element model. Both 96.5Sn/3.5Ag and 63Sn/37Pb solders are examined for their reliability by accelerated thermal cycling test (ATC) with temperatures ranging from -40degC to 150degC. This approach is used because solder joints are the weakest interconnection of the FCOB and the thermal stress induced low cycle fatigue due to mismatch in the coefficient of thermal expansion (CTE) is the key failure cause. The steady state forced convection and time- dependent elastic strain conditions are adopted. The reliability prediction is evaluated through the Kanchanomai model for 96.5Sn/3.5Ag solder balls and the Engelmaier model for 63Sn/37Pb solder balls, respectively. The simulation results indicate that the outmost solder joint has the largest Von Mises stress and strain for both lead-free and lead-based solders. The delamination between the chip and substrate is affected by the thermal-stress induced by the mismatched CTE. The reliability for lead-free solder 96.5Sn/3.5Ag can reach to 70% or above of the lead-based 63Sn/37Pb solder.

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing

The solder‐joint reliability of solder‐bumped wafer level chip scale package (WLCSP) on microvia build‐up printed circuit board (PCB) subjected to thermal cycling conditions is investigated in this study. The 62Sn36Pb2Ag solder joints are assumed to be: an elastic material; an elastic‐plastic material; and a creep material which obey the Garofalo‐Arrhenius steady‐state creep constitutive law. The stress and strain in the corner solder joint of the WLCSP assembly are presented and compared for these three material models. Also, the results presented herein will be compared with that from creep analysis of the WLCSP on PCB without microvia build‐up layer.

Recently the package market is demanding the smaller package size and the lower impedance electrical path with a short interconnection. The wafer level chip scale package is one of them, which has the solution of the market needs above. However, WLCSP technology is still not fully accepted on the large device size that is larger than 5mm × 5mm. It needs to overcome 2nd level reliability issue on both solder joint and drop reliability test. To improve 2nd level reliability, we need to apply the longer stand–off design such as Cu –post and double solder ball instead of single solder ball, and low modulus material on polymer layer under the solder pad for releasing thermal stress which result in the solder joints crack due to CTEs (Coefficient of Thermal Expansion) mismatch between organic PCB and WLCSP. In this paper, the double ball structure is introduced as one of them can provide the longer stand off. In addition of improving 2nd level reliability and drop test it may need to apply different solder ball component properties to increase Thermal cycling and drop test. The WLCSP structured a double solder ball showed a better 2nd level reliability result. This paper describes the molding process for double ball process and 2nd level reliability by solder property variation.

Flip chip ball grid array (FCBGA) is one of the most broadly used package types in different types of electronic packages. In a FCBGA package, the die/ silicon is flipped and attached to substrate with help of copper pillars. The material property coefficient of thermal expansion (CTE) mismatch between die/ silicon and substrate materials like core, dielectric material results in package thermal warpage and may lead to thermo-mechanical related failures in electronic packages. CTE can be defined as the rate at which a material expands with change in the temperature. Material expansion increases with a higher CTE. The CTE of die/ silicon is lower than the overall CTE of organic substrate. During reflow, as an electronic package cools down it warps in a convex or crying shape which indicates positive package warpage, and as the electronic package heats up it warps in a concave or smiling shape which indicates negative package warpage. Induced thermal warpage during the electronic package reflow assembly process is an important factor affecting the package assembly and thermo-mechanical reliability of FCBGA packages; therefore, precise package thermal warpage prediction is one of the most significant parameters for the electronic package design processes. In this study, the effect of different electronic package parameters (core material CTE, core thickness, package type) of the FCBGA package on its warpage are assessed by using finite element analysis (FEA) mechanical simulation methodology. A bare die FCBGA package having substrate core material with lower coefficient of thermal expansion (CTE) shows lower package warpage as the mismatch between die/ silicon and substrate core material CTE becomes dominant factor to drive the package warpage. To understand the package warpage trend, warpage is evaluated at room temperature &amp; high/ reflow temperature. The package warpage trend is reversed for larger FCBGA packages with stiffener ring. Substrate core material with higher CTE shows lower package warpage as CTE mismatch between substrate core material and stiffener ring material (steel/copper) CTE becomes the dominant factor to drive the package warpage. The counter intuitive package warpage data from mechanical simulation is compared with shadow-moire test data and it shows good correlation and validates the simulations findings. Based on this work, it is recommended that a thorough investigation for large size packages be conducted before choosing packaging materials. This work shall provide new insights for package designers to optimize thermal warpage and stress during package initial design phase.

The solder-joint reliability of a low-cost wafer-level chip scale package (WLCSP) on printed circuit board (PCB) under thermal fatigue is studied. The solder joints are subjected to thermal cycling and their crack lengths at different thermal cycles are measured. Also, the stress intensity factors at the crack tip of different crack lengths in the corner solder joint are determined by fracture mechanics with finite element method. Furthermore, an empirical equation for predicting the thermal-fatigue life of flip chip solder joints is proposed.

FeNi alloy is considered a possible substitute for Cu as under bump metallization (UBM) in wafer level package (WLP) since it forms very thin intermetallic compound (IMC) layer with Pb-free solder in the reflow process. In this paper, WLPs with FeNi and Cu UBM were fabricated and their board level reliabilities were studied comparatively. The WLP samples assembled on the printed circuit board (PCB) were subjected to temperature cycling and drop tests according to JEDEC standards. The results showed that the reliability of WLP with FeNi UBM was a little lower than that with Cu UBM. The main failure modes for both FeNi and Cu UBM samples in temperature cycling test were the crack in IMC or solder ball on PCB side. And detachments between UBM and the redistribution layer (RDL) were also observed in Cu UBM WLPs. In drop test, the crack of RDL was found in all failed FeNi UBM samples and part of Cu UBM ones, and the primary failure mode in Cu UBM samples was the crack of IMC on PCB side. In addition, the finite element analysis (FEA) was carried out to further understand the difference of the failure modes between the FeNi UBM samples and the Cu UBM samples. The high stress was observed around the UBM and the pad on PCB in the temperature cycling model. And the maximum stress appeared on the RDL in the drop simulation, which was obviously larger than that on the pad. The FEA results showed that the introduction of FeNi UBM increased the stress levels both in temperature cycling and drop tests. Thus, the FeNi alloy cannot simply replace Cu as UBM in WLP without further package structural optimization.

Printed circuit boards (PCB)and SMD packages are made from different materials which coefficients of thermal expansion can differ much. Hence, under thermal load, e.g. board assembly or at field conditions, PCB and package deformation and deviation from the initial state often occur as warpage. During board assembly this warpage can cause failures such as open solder joints and/or shorts of solder joints. In this paper, the use the of shadow moire technique will be introduced for capturing the warpage under thermal loads. Measurement results of single substrates and a selected BGA package will be shown. Furthermore, a design process for PCBs to be applied for investigation of the influence of assembly process parameter will be described. It is assumed that the applied variations and their influence on the assembly quality are linked by the equilibrium of mechanical forces between PCB, BGA and solder joint. Additionally, it is assumed that mechanical stress - especially in out-of-plane direction-may occur in the solder joints. These thoughts apply for soldering process as well as temperature cycling conditions. A finite element model was implemented to analyze the stress for the selected BGA under defined conditions and to investigate warpage impacts on reliability. Finally, a novel approach to measure the electrical functionality will be introduced addressing BGAs under test which come with a high number of connections.

Solder joints provide mechanical support, and electrical and thermal interconnection between packaging levels in microelectronics assemblies. Proper functioning of these interconnections and the reliability of the electronic packages depend largely on the mechanical properties of the solder joints. Lead free solders typically provide excellent thermo-mechanical properties and are commonly used as interconnections in electronic packages. However, the exposure of lead free solder joints to complicated thermal histories can degrade their mechanical behavior. For example, aging of lead free solders at high temperature leads to microstructural evolution resulting in reduced mechanical properties and increased creep deformations. Previous investigations on mechanical characterization of lead free solders have mainly emphasized mechanical testing at temperatures up to 125 °C. However, many electronic products are deployed in harsh environment applications including well drilling, geothermal energy, automotive power electronics, and aerospace engines, where solders are exposed to very high temperatures from 125-200 °C. Mechanical properties of lead free solders at elevated temperatures are limited.In this work, we have explored Mechanical behavior and aging effects in SAC305 (96.5Sn-3.0Ag-0.5Cu) solder joints at several extreme high testing temperatures (T = 125, 150, 175, and 200 °C) using the method of nanoindentation. A special high temperature stage and test protocols were used within the nanoindentation system to carefully control the testing temperature, and to make the measurements insensitive to thermal drift problems. Solder joints were extracted from 14 x 14 mm PBGA assemblies (0.8 mm ball pitch, 0.46 mm ball diameter) that were built as part of the iNEMI Characterization of Pb-Free Alloy Alternatives Project. Since the properties of SAC solder joints are highly dependent on crystal orientation, polarized light microscopy was utilized to determine the orientation of the tested joints. For all the experiments, only single grain solder joints were used to avoid introducing any unintentional variation from changes in the crystal orientation across the joint cross-section.To study aging effects, solder joints were preconditioned for 0, 1, 5, 10, and 30 days at T = 125 °C in a box oven. Nanoindentation testing was then performed on the aged specimens at four different test temperatures (T = 125, 150, 175, and 200 °C) to extract the elastic modulus, hardness, and creep performance of the aged material. Throughout this study, a constant force of 10 mN was applied for 900 seconds to monitor the creep displacements and measure the creep strain rate as a function of both temperature and prior aging conditions.As expected, our results have shown that mechanical properties and creep strain rate of solder joints are highly dependent on the test temperature and degrade significantly as the temperature increases. In particular, the aging induced degradation rates for high temperature testing (175-200 °C) were about 10000X than those observed at 125 °C. In addition, the effects of aging on solder joints properties become much more significant as the aging time and test temperature increases.

Effect of rare earth Ce on the fatigue life of SnAgCu solder joints in WLCSP device using FEM and experiments

Pin-through-hole (PTH) connection is one of the most common types of connection between components and circuit board. Taking the printed circuit board (PCB) of the typical electronic product air conditioner as research object, thermal fatigue behavior and failure mechanism of the through-hole solder joints were investigated by accelerated aging experiments and finite element analysis (FEA). Results showed that, besides that of the coefficient of thermal expansion (CTE) mismatch between the materials in the solder joint assembly, the influence of solder joint structure and component weight the pin supporting on the cumulative damage to solder joints were indispensable. Compared with the typical supported-hole solder joints, solder joints for this paper were more prone to the damage as component pin peeling off solder. And fatigue lives of solder joints decreased with component weight increasing. The solder joint lives calculated by FEA were between 1300∼1600 cycles, which agreed well with the experimental results.

A plastic chip-scale package (CSP) smaller than conventional packages has been developed and applied to ATM switching systems. The package uses a low-cost glass-epoxy substrate. As glass epoxy is widely used in the printed circuit boards (PCBs) of ATM switching systems, its use in the CSPs mounted on a PCB reduces the difference in thermal expansion between PCB and CSPs, thus lengthening CSP life. The power plane, ground plane, and thermal vias of the CSP are designed to offset the increased thermal resistance due to the CSP's smaller size. Simulation showed a thermal resistance for this CSP with copper layers and thermal vias of as much as 22% less than that of a CSP with no copper layers or thermal vias. A six-layer test board mounting four CSPs was used to simulate a sub-board for ATM switching systems. The thermal resistance of the two CSPs located downstream was about 10% higher than that of the two located upstream. Two CSPs were developed for two types of application-specific ICs: a bus interface controller (BIC) and a peripheral interface circuit (PIC). Both CSPs were 18 mm square with a 0.8 mm outer solder-ball pitch and 256 outer balls. These CSPs occupied areas about 87% and 68% smaller than those of a conventional pin grid array (PGA) and quad flat package (QFP) respectively. The junction temperature of both CSPs satisfied the thermal conditions. These high-performance CSPs are thus attractive for use in ATM switching systems.