Structured "truncated golomb code" for context-based adaptive VLC

The recent H.264 video coding standard adopted context-based adaptive variable length coding (CAVLC) as the entropy coding tool. By combining adaptive variable length coding (VLC) with context modeling, we can achieve a high degree of redundancy reduction. However, CAVLC in H.264 has a problem that correctness of VLC table prediction is low. In this paper, we propose a new VLC table prediction algorithm using both the correlation of coding mode and the statistics of mode distribution in both intra and inter frames. Experimental results show that the proposed algorithm reduces the bit rate by 0.94% on average.

As the most commonly used entropy coding method of H.264, CAVLC (context-based adaptive variable length coding) has been widely utilized for information hiding. Various information hiding methods directly manipulate CAVLC coefficients, which are reported to be of high payload and low computational complexity. However, things are quite different in real applications. This paper addresses two misconceptions about them: (1) The CAVLC coefficients can be modified without re-encoding process. In fact, direct modifications of the number of non-zero coefficients will change the corresponding code tables for adjacent blocks and result in decoding errors. (2) CAVLC codewords can be indiscriminately substituted. Actually, it will cause serious distortion drifts. In addition, considering steganographic security, a detection strategy is proposed based on statistical analysis of some CAVLC-based methods.

In general, context-based adaptive variable length coding (CAVLC) decoding in H.264/AVC standard requires frequent access to the unstructured variable length coding tables (VLCTs) and significant memory accesses are consumed. Heavy memory accesses will cause high power consumption and time delays, which are serious problems for applications in portable multimedia devices. We propose a method for high-efficiency CAVLC decoding by using a program instead of all the VLCTs. The decoded codeword from VLCTs can be obtained without any table look-up and memory access. The experimental results show that the proposed algorithm achieves 100% memory access saving and 40% decoding time saving without degrading video quality. Additionally, the proposed algorithm shows a better performance compared with conventional CAVLC decoding, such as table look-up by sequential search, table look-up by binary search, Moon’s method, and Kim’s method.

The H.264 video coding standard has been widely applied to multimedia data transmission. To prevent the contents of video from being recognized by someone unauthorized, providing sufficient security to H.264 has become more and more important. In this thesis, an improved H.264/AVC video encryption method is proposed. As compared with the Shahid’s method, more data are encrypted. And this makes the outcome more desirable. In the proposed scheme, selective encryption (SE) is performed in the motion vector difference (MVD), delta quantization parameter (delta QP), and the context-based adaptive variable length coding (CAVLC) modules. Owing that the encrypted stream should be decoded correctly before decryption, a format-compliant method is presented. Furthermore, in order to keep the bitrate unchanged, keeping the same stream length is another important characteristic of our proposed scheme. Since there is no escalation in bitrate, the proposed encryption algorithm is suitable for real-time multimedia streaming over heterogeneous networks. The encrypting key is generated by using the advanced encryption standard (AES) algorithm, and every frame has its own unique key. Four benchmark video sequences with different combinations of motion, texture and objects were used for experimental evaluation of the proposed scheme. The structural similarity (SSIM) index, a reference value to image quality, of the proposed scheme is 0.202 which is lower than 0.233 of the Shahid’s scheme. The key security is shown reliable under the test of only 1 bit change. The extra computation needed by our scheme is less than 0.5%, so it is feasible for real-time transmission. The above performance on security and sensitivity demonstrates that our proposed scheme is a good candidate for practical applications.

A memory and speed efficient CAVLC (context adaptive variable length coding) decoder for H.264/AVC baseline profile is proposed. Because the CAVLC consists of a kind of bit-level operations, general processor (like RISC or MIPS) and DSP incorporating multiple parallel arithmetic units (like SIMD or VLIW) are ineffective to decode it. Though the dedicated hardwires are very effective to decode the CAVLC, they are expensive and not programmable. Also, the size of the CAVLC lookup table is more than 400 bytes. Demand for highly flexible and fast implementations and lower memory size for CAVLC decoding is rising nowadays. The four instructions--ShowBits, GetBits, FlushBits and LeadingBits, are designed after the exploiting of the functions coverage. In order to reduce the codewords matching miss and the lookup table size, a new grouping, remainder generation method and a merged lookup table (LUT) are used; and the specific group decoding instruction GroupDecoding is also presented. In summary, a based instruction set level acceleration with the codewords group partition hardware architecture is proposed to speed up the CAVLC decoding. Based on those instructions and the hardware platform, the CAVLC decoding can be significantly accelerated compared with the method in H.264 reference software. Simulation results show that the architecture is sufficient for the CAVLC decoding of 30 frames HDTV (1902 x 1080 pixels) per second.

H.264/AVC entropy decoder complexity analysis and its applications

This paper presents a low-cost high-performance H.264/AVC SVC decoder with multi-symbol prediction context-based adaptive variable length coding (CAVLC) for advanced T-DMB receiver. Proposed multi-symbol prediction CAVLC mainly consists of a simple arithmetic operation unit with reduced look-up tables and a leading zero detector. We also propose a multi-symbol run_before decoder and it decodes more than 2.5 symbols in a cycle. Gate count of a H.264/AVC SVC decoder is about 1,300K gates when synthesized with 0.18 um CMOS process and it can be operated at 120 MHz clock frequency. For the verification of a H.264/AVC SVC decoder chip, prototype mobile movie player systems have been implemented using a 7 inch LCD and USB controller.

Context-based adaptive variable length coding (CAVLC) of H.264/AVC was originally designed for quantized transform coefficients in lossy video coding, and as such does not yield adequate performance in lossless video coding. In this paper, we propose an improved CAVLC for lossless intra coding. Considering statistical differences of residual data in lossy and lossless coding, we design a new CAVLC encoding algorithm. Experimental results show that the proposed method provides approximately 7.6% bit savings, compared to the current H.264/AVC FRExt high profile.

In H.264/AVC, the Context-based Adaptive Variable Length Coding (CAVLC) is used for lossless compression. Direct table-lookup implementation requires higher cost because it employs a larger memory to produce the encoded results. A carefully reduced table is constructed and used for encoding in the design. With the helps of symbol mapping and codeword generating modules, our encoder can generate the CAVLC bitstream accurately. Compared with those previous designs, our method reduces up to 81% of memory size for storing those VLC tables used in H.264/AVC. Thus, our design is a good candidate for low-cost CAVLC.

The paper presents a VLSI prototype for context-based adaptive variable length coding (CAVLC). This scheme is a part of the lossless compression process in the MPEG-4 Part 10 standard. It is applied to the quantized transform coefficients of the luminance component during the entropy coding process. In combination with previous transformations and quantizations, it can result in significantly increased compression ratio. The developed architecture is prototyped and simulated using ModelSim 5.4/spl reg/. It is synthesized using Synplify Pro 7.1/spl reg/. The results show that the architecture satisfies the real-time constraints required by different digital video applications.

In this paper, we propose hardware architecture for a high-speed context-adaptive variable length coding (CAVLC) decoder in H.264. In the CAVLC decoder, the codeword length of the current decoding block is used to determine the next input bitstreams (valid bits). Since the computation of valid bits increases the total processing time of CAVLC, we propose two techniques to reduce processing time: one is to reduce the number of decoding steps by introducing a lookup table, and the other is to reduce cycles for calculating the valid bits. The proposed CAVLC decoder can decode 1920×1088 30 fps video in real time at a 30.8 MHz clock.

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44-48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

Context-based adaptive variable-length coding (CAVLC) is a new and important feature of the latest video coding standard, H.264/AVC. The direct VLSI implementation of CAVLC modified from the conventional run-length coding architecture will lead to low throughput and utilization. In this brief, an efficient CAVLC design is proposed. The main concept is the two-stage block pipelining scheme for parallel processing of two 4 times 4 blocks. When one block is processed by the scanning engine to collect the required symbols, its previous block is handled by the coding engine to translate symbols into bitstream. Our dual-block-pipelined architecture doubles the throughput and utilization of CAVLC at high bit rates. Moreover, a zero skipping technique is adopted to reduce up to 90% of cycles at low bit rates. Last but not least, Exp-Golomb coding for other general symbols and bitstream encapsulation for the network abstraction layer are integrated with CAVLC as a complete H.264/AVC baseline profile entropy coder. Simulation shows that our design is capable of real-time processing for 1920 times 1088 30-fps videos with 23.6 K logic gates at 100 MHz

In H.264, the context-based adaptive variable length coding (CAVLC) is used for lossless compression. Direct table-lookup implementation requires higher cost because it employs a larger memory to produce the encoded results. In this letter, we present a more efficient technique for CAVLC implementation. Compared with those previous CAVLC chips, our design requires the lowest hardware cost.

H.264/AVC offers critical advantages over other video compression schemes at the price of increased computational complexity. The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binary coder, which is the last stage of the video coder. The module conforms to H.264/AVC High Profile and supports two binary coding modes: context adaptive binary arithmetic coding (CABAC) and context adaptive variable-length coding (CAVLC). The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. Five versions of the arithmetic coding path are developed to study the area/performance tradeoff related to parallel symbol encoding. The implementation results show that the parallel symbol encoding allows higher efficiency. The whole architecture of the binary coder is described in VHDL and synthesized for different configurations to show the implementation cost of some coding options. For both CAVLC and CABAC modes, the architecture achieves the similar throughput able to support HDTV in real time.