Superfast Solution of Real Positive Definite Toeplitz Systems

The oversampled Gabor transform is more effective than the critically sampled one in many applications. The biorthogonality relationship between the analysis window and the synthesis window of the Gabor transform represents the completeness condition. However, the traditional discrete cosine transform (DCT)-based real-valued discrete Gabor transform (RGDT) is available only in the critically sampled case and its biorthogonality relationship for the transform has not been unveiled. To bridge these important gaps, this paper proposes a novel DCT-based RDGT, which can be applied in both the critically sampled case and the oversampled case, and their biorthogonality relationships can be derived. The proposed DCT-based RDGT involves only real operations and can utilize fast DCT algorithms for computation, which facilitates computation and implementation by hardware or software as compared to that of the traditional complex-valued discrete Gabor transform. This paper also develops block time-recursive algorithms for the efficient and fast computation of the RDGT and its inverse transform. Unified parallel lattice structures for the implementation of these algorithms are presented. Computational complexity analysis and comparisons have shown that the proposed algorithms provide a more efficient and faster approach for discrete Gabor transforms as compared to those of the existing discrete Gabor transform algorithms. In addition, an application in the noise reduction of the nuclear magnetic resonance free induction decay signals is presented to show the efficiency of the proposed RDGT for time-frequency analysis.

This paper describes and suggests the data visualization for real time power system operation based on energy management system. Because real time power system operation performs analysis of the vast amount of on-line data, the operators need intuitive data visualization to find out useful information in the big data. Especially, in emergency situation, the data visualization is able to assist the operators in handling the crisis quickly and efficiently. Therefore, this paper aims to improve displays of output of real time power system operation by visualizing on-line big data. Through this study, we can develop improved visualization technique for real time power system operation, which has highly readable displays of output and intuitive information.

A new preconditioning strategy for symmetric positive definite banded circulant and Toeplitz systems is described. The optimal tridiagonal preconditioner for tridiagonal circulant systems is modified and applied to both circulant and Toeplitz banded systems. The strategy is extended to block tridiagonal systems. The parallelisation aspects of the PCG algorithm are discussed.

Recent research presents a technique to enumerate all valid assignments of “twiddle factors” for power-of-two fast Fourier transform (FFT) flow graphs. Brute-force search employing state-of-the-art Boolean satisfiability (SAT) solvers can then be used to find FFT algorithms within this large solution space which have desirable characteristics. Surprisingly, this approach has discovered FFT algorithms requiring fewer operations than the split-radix algorithm even when all twiddle factors are nth roots of unity. This paper reviews and then extends this prior research to examine fast discrete convolution algorithms when implemented via FFT and inverse FFT (IFFT) algorithms. In particular, we find that the combination of FFT and IFFT algorithms in fast convolution permits greater freedom when selecting valid twiddle factor assignments. We exploit this freedom and use SAT solvers to find new fast convolution algorithms with the lowest operation counts known.

The fast algorithms of discrete sinusoidal transform of the fourth type (DST-IV) for small-length input data in the range of lengths from 2 to 9 are developed. Fast algorithms for short input data sequences are subsequently used as building blocks for designing fast algorithms of large-sized discrete transforms. Applying the fast DST-IV algorithms for small-size block processing can reduce overall system complexity and delay, allowing detailed signal processing. As a result of the literature review, two main approaches to developing fast discrete sine transform (DST) algorithms were identified, namely, the polynomial algebraic approach and the matrix factorization approach. In the paper, the last approach is exploited. A matrix-vector product expression of the DST-IV is the starting point for designing the fast algorithms. Then based on the repetition and arranging of the matrix elements, the factorisation of the matrices of coefficients of DST-IV is produced to reduce computational complexity. The correctness of the obtained algorithmic solutions was justified theoretically using a strict mathematical background of each of them. The elaborated algorithms were then further tested using MATLAB R2023b software to finally confirm their performance. The resulting factorizations of the DST-IV matrices reduce the number of multiplications by 63% but increase the number of additions by 8% on average in the range of signal sample numbers from 3 to 9. It has been observed that for even-length input sequences, the reduction in the number of multiplications is not as significant as for odd-length sequences. For some other well-known discrete trigonometric transforms (discrete Fourier transform, discrete Hartley transform) the opposite situation holds. The proposed DST-IV fast algorithms do not limit the length of the input data sequence to powers of two or three. The data flow graphs constructed for the proposed algorithms reveal their modular space-time structure suitable for VLSI implementation. Keywords: discrete sine transform; matrix factorization; fast algorithms; computational complexity; digital signal processing.

Background: Fast Fourier Transform (FFT) processor is the important method in Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Split-Radix Fast Fourier Transform (SRFFT) estimates the least number of multiplications compared to other FFT algorithm; hence SRFFT is the best for the implementation of low power FFT processor. Methods: In this paper, the proposed “pipelined 32-point Split-Radix Multi-path Delay Commutator (SFMDC) FFT” architecture is designed. The MDC architecture has advantages in reducing the low chip area and lower power consumption. The SR-FFT algorithm has changing the numbers of butterfly elements in successive stages. The 32-point SR-MDC FFT architecture is to determine the frequency transformation techniques. The Split-Radix FFT algorithm is based on radix-2 and radix-4 algorithm and it is related to mixed radix FFT. Findings: The performance evaluation of proposed architecture is determined through VLSI System. Less area, low power consumption and high speed are the main parameters in this design. The proposed structure provides high throughput rate and low hardware complexity. Improvements: The goal of this proposed work is to reduce the slices and LUTs and power consumption and also to enhance the performances of the FFT processor than the existing method. The proposed method has been evaluated by using ModelSim 6.3C and synthesis results has been validated by using Xilinx Plan ahead 12.4.

The time of delivering the embedded system solution to market is very important, because of the highly competitive market and demand of the consumer needs. In Real Time Operating System (RTOS) based embedded systems, the overall correctness of the embedded system depends on logically correct output within the specified time. Developing, testing and debugging of an RTOS based embedded system takes lots of time. The virtual platform provides the great advantage in developing, testing and debugging the RTOS based embedded system. This work describes the design and development of a reconfigurable virtual platform for real-time kernel. Eclipse IDE platform, NXP LPC-2129 target, OpenOCD have been chosen to develop this reconfigurable virtual platform for real-time kernels. For the selected target, GNU Toolchain has been configured as a plug-in in Eclipse IDE for both Windows and Linux to get own virtual platform. The μC/OS-II Board Support Package and the virtual timer for gdb debugger to support selected target has been developed and added in this virtual platform. This virtual platform facilitates the reconfiguration of the various RTOS such as μC/OS-II, DrRTOS and AVX. From the implementation of this design framework on real system, it can be concluded that the virtual platform increases the efficiency of the RTOS based applications. It gives the single solution for the developers to develop, execute, test, debug and verify the applications for various RTOS in a shorter span of time and with substantial reduction of developmental cost.

Predictive control has great potential in the home energy management domain. However, such controls need reliable predictions of the system dynamics as well as energy consumption and generation, and the actual implementation in the real system is associated with many challenges. This paper presents the implementation of predictive controls for a heat pump with thermal storage in a real single-family house with a photovoltaic rooftop system. The predictive controls make use of a novel cloud camera-based short-term solar energy prediction and an intraday prediction system that includes additional data sources. In addition, machine learning methods were used to model the dynamics of the heating system and predict loads using extensive measured data. The results of the real and simulated operation will be presented.

Hw/Sw Co-Design technique for 2D fast fourier transform algorithm on Zynq SoC

A parameterized modal analysis is proposed to evaluate power system small-signal stability and a simulation procedure using DIgSILENT programming language (DPL) is presented for this purpose. Modal analysis, or small-signal stability analysis, refers to the ability of a system to withstand small perturbations around an equilibrium point without reaching instability or displaying sustained oscillations. This is an important problem in real systems as sustained oscillations may cause mechanical failures in generating units and make the system vulnerable to the point of losing stability. In order to define the most critical scenario, the standard approach employed by the industry is to consider the system at its maximum loading. This chapter proposes that critical scenarios should be further sought as in even lighter loading conditions, low-frequency oscillations may dangerously appear. Using DPL, the system modal analysis is parameterized in order to search for critical operating points. To validate the importance of employing a parameterized modal analysis, a real case is studied: the Northern Chile Interconnected System. The obtained results applying parameterized modal analysis show that the system in a real operation only requires minor deviations from the programmed operating points to incur in dangerous low-frequency oscillations. These results validate the importance of searching for critical scenarios and DPL scripting is used to program the steps of the proposed analysis. The scripts and applications presented in this chapter set the basis for additional development to identify critical scenarios for modal analysis in other real systems.

A large family of signal processing techniques consist of Fourier-transforming a signal, manipulating the Fourier-transformed data in a simple way, and reversing the transformation.We widely use Fourier frequency analysis in equalization of audio recordings, X-ray crystallography, artefact removal in Neurological signal and image processing, Voice Activity Detection in Brain stem speech evoked potentials, speech processing spectrograms are used to identify phonetic sounds and so on.Discrete Fourier Transform (DFT) is a principal mathematical method for the frequency analysis.The way of splitting the DFT gives out various fast algorithms.In this paper, we present the implementation of two fast algorithms for the DFT for evaluating their performance.One of them is the popular radix-2 Cooley-Tukey fast Fourier transform algorithm (FFT) [1] and the other one is the Grigoryan FFT based on the splitting by the paired transform [2].We evaluate the performance of these algorithms by implementing them on the Xilinx Virtex-II pro [3], and FPGAs, by developing our own FFT processor architectures.Finally we show that the Grigoryan FFT is working faster than Cooley-Tukey FFT, consequently it is useful for higher sampling rates.At the same time we also confirm that Virtex-5 is better platform, for the same architectures, among all these for implementing Grigoryan FFT (FFT algorithm under evaluation), as Virtex-5 FPGAs give highest speed of operation for higher sampling rates of FFT.Operating at higher sampling rates is a challenge in DSP applications.

Fast algorithms for least-squares-based minimum variance spectral estimation

A new fast static security analysis algorithm, based on the interval analysis theory and probability theory, is proposed to improve the efficiency and accuracy of security analysis during power network interaction. In this paper, the characteristics of network interaction and uncertainty in the interaction process are illustrated firstly. After that the dimension reduction technique is employed in DC interval load flow calculation to determine the branch power flow efficiently. Then active power related contingency screening index is proposed, based on the DC interval analysis and the probability theory, which facilitates the screening of serious contingencies during the interactive process and improves the accuracy of contingency screening. Finally, cumulated and Gram-Charlier series expansion based AC probabilistic power flow is carried out for different operating scenarios during interactive time process. JS 1018-bus example system is introduced to validate the proposed method. Compared with traditional static security analysis, the proposed method can provide more efficient and accurate results for real time system operation.

A real-time operating system (RTOS) is software which ensures that time critical events are processed as efficiently as possible. In this paper, an attempt has been taken to develop a real time operating system, named Preemptive Real Time Operating System (pRTOS), in which all of the important issues regarding to a real time application have been considered. In this pRTOS, strictly preemptive scheduling algorithm has been used. This scheduling policy makes sure that important tasks are handled first and the less important later. The Bitmap technique has been used to find out the highest priority task from the unsorted ready list. The complexity of this technique for selecting the highest priority task is O(1), which is much faster than the linear search technique having complexity of O(n). This pRTOS can support 64 priority levels ranges from 0 to 63. In addition with this, it is a highly configurable RTOS. Moreover, it can be adopted in a board range of hardware platform, say, Intel x86, MIPS, Hitachi SH, Power PC and Strong ARM processors. This RTOS has been tested on Intel x86 and from the obtained result, it has been found that our developed pRTOS can be used for various application, say, for automated industrial systems, control-systems, high-tech electronics/electrical products and home applications.

Investigation and improvement of the Mini-Max Polynomial Approximation method for solving burnup equations