Syndrome based check node processing of high order NB-LDPC decoders

Non-binary low-density parity-check (NB-LDPC) codes can exhibit more considerable coding gain than their binary counterparts in numerous cases. To further exploit the benefit of NB-LDPC codes, in this letter, a novel type of non-binary LDPC codes, alterable subset non-binary LDPC (AS-NB-LDPC) codes, is proposed for reducing the peak-to-average power ratio (PAPR) of orthogonal frequency division multiplexing (OFDM) systems. Firstly, we design the alteration scheme of AS-NB-LDPC codes to make <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> -ary LDPC codes generate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> valid codewords through one alterable subset, and the codeword with the minimum PAPR is selected for transmission. Then inspired by the invertible subset for binary LDPC codes, the necessary and sufficient conditions for alterable subset generation are derived. Furthermore, we propose an improved progressive edge growth (PEG) construction method to obtain AS-NB-LDPC codes with favorable frame error rate (FER) performance. Simulation results verify the effectiveness of the proposed NB-LDPC codes.

Non-binary low-density parity-check (NB-LDPC) codes, defined over GF(q), have been extensively studied since analyzed by Davey and Mackay in 1998 [1]. It was demonstrated that the NB-LDPC code has superior error-correcting performance than the binary counterparts in algorithm-level investigation. However, it is hard to directly employ a high-throughput NB-LDPC decoder due to its high processing complexity and excessively long decoding latency. Based on the conventional extended min-sum (EMS) algorithm [2], which reduces the message size without losing the correcting power, we introduce a high-throughput but area-efficient NB-LDPC decoder handling multiple message elements at the same time. The previous variable node processing (VNP) is modified to accept the multiple message elements and to promote parallel processing eventually. For the efficient decoder design, the delay overheads are carefully optimized in the two-stage sorter. The prototype decoder for the (160, 80) NB- LDPC code is implemented in a 22nm FinFET technology, achieving the decoding throughput of 7 Gbps.

When the code is not long, non-binary low-density parity-check (NB-LDPC) codes can achieve better error-correcting performance than binary LDPC codes at the cost of higher decoding complexity. The recently developed iterative reliability-based majority-logic NB-LDPC decoding can achieve better performance-complexity tradeoffs than previous algorithms. Many existing NB-LDPC code construction schemes lead to quasi-cyclic or cyclic codes. In this paper, efficient low-complexity NB-LDPC decoder architectures are developed for these two types of codes based on the newly proposed iterative hard reliability-based majority-logic decoding (IHRB-MLGD). Particularly, novel schemes are designed to keep a small proportion of messages in order to reduce the memory requirement without causing noticeable performance loss. Moreover, a shift-message structure is proposed by using memories concatenated with variable node units to enable efficient partial-parallel decoding for cyclic NB-LDPC codes. Compared to previous decoders based on the Min-max algorithm, the proposed IHRB-MLGD decoder architectures can achieve tens of times higher efficiency for codes with similar length and rate with moderate coding gain loss.

Short cycles in a nonbinary low-density parity-check (NB-LDPC) code may be even more harmful to its performance if they do not satisfy the so-called full rank condition (FRC). This is because they may induce low-weight codewords or absorbing sets in that case. Thus, it is important to count the number of short cycles not satisfying the FRC as well as the number of short cycles for analyzing the performance of an NB-LDPC code. In this paper, we first develop a novel message-passing algorithm and identify how it is related to the FRC. We then propose a low-complexity algorithm for counting the number of short cycles not satisfying the FRC in an NB-LDPC code, as well as the number of short cycles. Finally, we propose a low-complexity algorithm for designing an NB-LDPC code with low error floor. Depending on the modulation scheme, the codes constructed by the proposed design algorithm have similar or slightly worse performance, compared with those constructed via the method by Poulliat et al. However, the proposed design algorithm does not require a cycle enumeration algorithm with high complexity, and therefore is feasible even in the case of large code length, say ${\geq}5000$ .

Forward error correction is an essential part of digital communication systems. Non-binary low-density parity-check (NB-LDPC) codes have an excellent communications performance for short block lengths. The higher the field size is, the better the communications performance is. Non-binary LDPC codes can outperform all other state-of-the-art code classes. However, the algorithmic decoding complexity grows with the field size. For an intended, future use of these codes in real systems, an efficient hardware implementation is mandatory. Hardware architectures for binary LDPC codes are well investigated, but efficient implementation of non-binary LDPC decoders is still an open field. To the best of our knowledge, this paper studies for the first time the hardware implementation costs for non-binary LDPC decoders with Galois field sizes of 4, 16 and 256 on FPGA and a 65nm ASIC technology.

In this paper, we first describe a 9-symbol non-uniform signaling scheme based on Huffman code, in which different symbols are transmitted with different probabilities. By using the Huffman procedure, prefix code is designed to approach the optimal performance. Then, we introduce an algorithm to determine the optimal signal constellation sets for our proposed non-uniform scheme with the criterion of maximizing constellation figure of merit (CFM). The proposed nonuniform polarization multiplexed signaling 9-QAM scheme has the same spectral efficiency as the conventional 8-QAM. Additionally, we propose a specially designed GF(32) nonbinary quasi-cyclic LDPC code for the coded modulation system based on the 9-QAM non-uniform scheme. Further, we study the efficiency of our proposed non-uniform 9-QAM, combined with nonbinary LDPC coding, and demonstrate by Monte Carlo simulation that the proposed GF(23) nonbinary LDPC coded 9-QAM scheme outperforms nonbinary LDPC coded uniform 8-QAM by at least 0.8dB.

The problem of low-complexity linear programming (LP) decoding of nonbinary low-density parity-check (LDPC) codes is considered, and an iterative LP decoding algorithm is presented. Results that were previously derived for binary LDPC codes are extended to the nonbinary case. Both simple and generalized nonbinary LDPC codes are considered. It is shown how the algorithm can be implemented efficiently using a finite-field fast Fourier transform. Then, the convergence rate of the algorithm is analyzed. The complexity of the algorithm scales linearly in the block length, and it can approximate, up to an arbitrarily small relative error, the objective function of the exact LP solution. When applied to a typical code from an appropriate nonbinary LDPC code ensemble, the algorithm can correct a constant fraction of errors in linear (in the block length) computational complexity. Computer experiments with the new iterative LP decoding algorithm show that, in the error floor region, it can have better performance compared to belief propagation decoding, with similar computational requirements.

Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.

Non-binary low-density parity-check (LDPC) codes have been shown to attain near capacity error correcting performance in noisy wireless communication channels. It is well known that these codes require a very large number of operations per-bit to decode. This high computational complexity along with a parallel decoder structure makes graphics processing units (GPUs) an attractive platform for acceleration of the decoding algorithm. The seemingly random memory access patterns associated with decoding are generally beneficial to error-correcting performance but present a challenge to designers who want to leverage the computational capabilities of the GPU. In this paper we describe the design of an efficient decoder implementation based on GPUs and a corresponding set of powerful non-binary LDPC codes. Using the belief propagation algorithm with a sequential message updating scheme it is shown that we are able to exploit parallelism inherent in the decoding algorithm while decreasing the number of decoding iterations required for convergence.

In this paper we design non-uniform bit-wise puncturing distributions for irregular non-binary LDPC (NB-LDPC) codes. The puncturing distributions are optimized by minimizing the decoding threshold of the punctured LDPC code, the threshold being computed with a Monte-Carlo implementation of Density Evolution. First, we show that Density Evolution computed with Monte-Carlo simulations provides accurate (very close) and precise (small variance) estimates of NB-LDPC code ensemble thresholds. Based on the proposed method, we analyze several puncturing distributions for regular and semi-regular codes, obtained either by clustering punctured bits, or spreading them over the symbol-nodes of the Tanner graph. Finally, optimized puncturing distributions for non-binary LDPC codes with small maximum degree are presented, which exhibit a gap between 0.2 and 0.5 dB to the channel capacity, for punctured rates varying from 0.5 to 0.9.

In this paper, we propose a construction method for two-level quantum error-correcting codes via non-binary LDPC codes over an extended field of order 2p, p an integer p > 1. The proposed quantum error-correcting codes are based on binary quasi-cyclic LDPC codes which have almost achieved a “Bounded Distance Decoding (BDD)” limit but have not surpassed the limit yet. Quantum codes constructed from the proposed method surpass the BDD limit. Furthermore the codes outperform the efficiently-decodable state-of-the-art quantum codes.

This paper considers the ensemble enumerators of protograph-based nonbinary (PB NB) LDPC codes. Equipped with combinatorial definitions extended to the nonbinary domain, ensemble enumerators of codeword weight, trapping set size and stopping set size are calculated. The exact enumerators are presented in the finite-length regime, and the corresponding growth rates are calculated in the asymptotic regime. Our results can provide useful analytical tools for a range of communication and storage applications employing nonbinary LDPC codes.

Low-Density Parity-Check (LDPC) codes are a well known Error Correction Code family used for instance, in wireless and satellite communication links. Error correction performance of LDPC codes was further enhanced by extending it to higher order Galois fields, giving rise hence to the so-called non-binary LDPC codes (NB-LDPC). Error correction performance improvement (CCSDS 2014) is the main reason behind the adoption by the Consultative Committee for Space Data Systems (CCSDS) of the NB-LDPC codes in the experimental specification for the future next generation uplinks (CCSDS 2014, 2015). The high error correction efficiency for short frames make NB-LDPC codes a good candidate for IoT applications. However, the performance gain comes at the expense of a high decoding computational complexity (CCSDS 2014; Conde-Canencia et al. 2009). In this paper, an x86 multicore NB-LDPC decoder implementation is provided. This decoder that implements the FFT-SPA algorithm provides a throughput improvement of about 1.3 × to 2.7 ×, a latency reduction of more than 95% and a power consumption halved in comparison with the most efficient works on GPU (Graphics Processing Unit) device. Indeed, an efficient memory mapping and computation optimizations on the x86 architecture enable to achieve a higher decoding throughput than the GPU-based in similar experimental setup. Consequently, the throughput efficiency, the low processing latency associated with a low power consumption makes this proposed multicore implementation practical and attractive for real time implementations of NB-LDPC decoders in future SDR or Cloud-RAN systems for CCSDS standard and IoT applications.

This paper studies an iterative multiuser detection and decoding for nonbinary low density parity check (LDPC) coded multicarrier M-ary frequency shift keying (MC MFSK) multiple access system to increase system spectral efficiency under specific signal-to-noise ratio. At multiuser detection side, soft metric for each symbol is quantized to 2 levels (2L) or 3 levels (3L) and then pass to the decoder. When the soft output of a symbol from decoder exceeds a threshold, the user is declared as a reliable symbol. The reliable information is fed back to the detection side and updates the symbol soft output when iterative processing is carried out. Numerical results show that system spectral efficiency is improved for 3L system over Rayleigh fading. Index Terms - Nonbinary LDPC codes, Multicarrier MFSK, Multiple Access.

In multiple-input multiple-output (MIMO) transmission systems, the channel state information (CSI) at the transmitter can be used to add linear precoding to the transmitted signals in order to improve the performance and the reliability of the transmission system. This paper investigates how to properly join precoded closed-loop MIMO systems and nonbinary low density parity check (NB-LDPC). Theqelements in the Galois field, GF(q), are directly mapped toqtransmit symbol vectors. This allows NB-LDPC codes to perfectly fit with a MIMO precoding scheme, unlike binary LDPC codes. The new transmission model is detailed and studied for several linear precoders and various designed LDPC codes. We show that NB-LDPC codes are particularly well suited to be jointly used with precoding schemes based on the maximization of the minimum Euclidean distance (max-dmin) criterion. These results are theoretically supported by extrinsic information transfer (EXIT) analysis and are confirmed by numerical simulations.