Synetgy

Many-Accelerator (MA) systems have been introduced as a promising architectural paradigm that can boost performance and improve power of general-purpose computing platforms. In this paper, we focus on the problem of resource under-utilization, i.e. Dark Silicon, in FPGA-based MA platforms. We show that except the typically expected peak power budget, on-chip memory resources form a severe under-utilization factor in MA platforms, leading up to 75 percent of dark silicon. Recognizing that static memory allocation—the de-facto mechanism supported by modern design techniques and synthesis tools—forms the main source of memory-induced Dark Silicon, we introduce a novel framework that extends conventional high level synthesis (HLS) with dynamic memory management (DMM) features, enabling accelerators to dynamically adapt their allocated memory to the runtime memory requirements, thus maximizing the overall accelerator count through effective sharing of FPGA's memories resources. We show that our technique delivers significant gains in FPGA's accelerators density, i.e. 3.8 $\times$ , and application throughput up to 3.1 $\times$ and 21.4 $\times$ for shared and private memory accelerators.

Real-time understanding of surrounding environment is an essential yet challenging task for autonomous driving system. The system must not only deliver accurate result but also low latency performance. In this paper, we focus on the task of fast-and-accurate semantic segmentation. An efficient and powerful deep neural network termed as Driving Segmentation Network (DSNet) and a novel loss function Object Weighted Focal Loss are proposed. In designing DSNet, our goal is to achieve the best capacity with constrained model complexity. We design efficient and powerful unit inspired by ShuffleNet V2 and also integrate many successful techniques to achieve excellent balance between accuracy and speed. DSNet has 0.9 million of parameters, achieves 71.8% mean Intersection-over-Union (IoU) on Cityscapes validation set, 69.3% on test set, and runs 100+ frames per second (FPS) at resolution 640 × 360 on NVIDIA 1080Ti. In order to improve performance on minor and hard objects which are crucial in driving scene, Object Weighted Focal Loss (OWFL) is proposed to deal with the serious class imbalance issue in pixel-wise segmentation task. It could effectively improve the overall mean IoU of minor and hard objects by increasing loss contribution from them. Experiments show that DSNet performs 2.7% points higher on minor and hard objects compared with fast-and-accurate model ERFNet under similar accuracy. These traits imply that DSNet has great potential for practical autonomous driving application.

We explore how to organize large text databases hierarchically by topic to aid better searching, browsing and filtering. Many corpora, such as internet directories, digital libraries, and patent databases are manually organized into topic hierarchies, also called taxonomies. Similar to indices for relational data, taxonomies make search and access more efficient. However, the exponential growth in the volume of on-line textual information makes it nearly impossible to maintain such taxonomic organization for large, fast-changing corpora by hand. We describe an automatic system that starts with a small sample of the corpus in which topics have been assigned by hand, and then updates the database with new documents as the corpus grows, assigning topics to these new documents with high speed and accuracy. To do this, we use techniques from statistical pattern recognition to efficiently separate the feature words, or discriminants, from thenoise words at each node of the taxonomy. Using these, we build a multilevel classifier. At each node, this classifier can ignore the large number of “noise” words in a document. Thus, the classifier has a small model size and is very fast. Owing to the use of context-sensitive features, the classifier is very accurate. As a by-product, we can compute for each document a set of terms that occur significantly more often in it than in the classes to which it belongs. We describe the design and implementation of our system, stressing how to exploit standard, efficient relational operations like sorts and joins. We report on experiences with the Reuters newswire benchmark, the US patent database, and web document samples from Yahoo!. We discuss applications where our system can improve searching and filtering capabilities.

In recent years, Natural Language Processing (NLP) has gradually become a heated topic in research area, and Transformer-based pretrained models (the most widely used is BERT) have achieved state-of-the-art results in many NLP tasks. But since Transformer-based pretrained models always contain extensive parameters, and consume much time in computing, it is really difficult to employ them on resource-limited embedded platform or mobile devices. To resolve this issue, we utilize the ALBERT model with the improved early exit method (ELBERT) and propose an efficient VLSI architecture for it in an algorithm and hardware co-design way. First of all, by using the quantization and encoder-level parameter sharing techniques, the storage space for saving BERT is reduced from 1208.88 MB to 20.99MB with little accuracy loss, which makes it possible to store all the weights on-chip. Secondly, we present a hardware-friendly design for the improved early-exit method. In contrast to the original ALBERT implementation, the accelerator combining ALBERT model with improved early exit can obtain a speed-up of 4.59x. Thirdly, owing to our efficient hardware design, experiments demonstrate that our FPGA accelerator can achieve a performance-per-watt of 1.29 fps/W, which is 25.97x over NVIDIA 2080 Ti GPU. On the whole, we introduce an efficient accelerator on FPGA with compressed BERT and a hardware-oriented early exit method, which solves the challenge to deploy the BERT to resource-constrained edge platforms with strict latency and memory requirements.

Deep convolutional neural networks (ConvNets) have achieved the state-of-the-art performance on many real-world applications. However, significant computation and storage demands are required by ConvNets. Spiking neural networks (SNNs), with sparsely activated neurons and event-driven computations, show great potential to take advantage of the ultra- low power spike-based hardware architectures. Yet, training SNN with similar accuracy as ConvNets is difficult. Recent researchers have demonstrated the work of converting ConvNets to SNNs (CNN-SNN conversion) with similar accuracy. However, the energy-efficiency of the converted SNNs is impaired by the increased classification latency. In this paper, we focus on optimizing the classification latency of the converted SNNs. First, we propose a restricted output training method to normalize the converted weights dynamically in the CNN-SNN training phase. Second, false spikes are identified and the false spike inhibition theory is derived to speedup the convergence of the classification process. Third, we propose a temporal max pooling method to approximate the max pooling operation in ConvNets without accuracy loss. The evaluation shows that the converted SNNs converge in about 30 time-steps and achieve the best classification accuracy of 94% on CIFAR -10 dataset.

Railway platform clearance is directly related to the safe operation of trains and the personal safety of passengers. Precise, efficient, and real-time platform clearance inspection is of importance to the safety of railway operations. Considering the shortcomings of the contact measurement method, such as low efficiency, low precision, and many manual operations, a platform clearance measurement system based on monocular computer vision assisted with structured light is proposed. The coordinate of corner points from the calibration ruler is determined by the LSD algorithm to compute a transformation matrix from Image Coordinate System (ICS) to World Coordinate System (WCS). Then, based on homography transformation, the world coordinates of the platform are obtained by the transformation matrix; and used to calculate different types of clearances. The experiments show that the precision can reach 5mm by using the system. It can effectively meet the requirements of railway operation and have a broad prospect.

Deep Learning has established itself to be a common occurrence in the business lexicon. The unprecedented success of deep learning in recent years can be attributed to: an abundance of data, availability of gargantuan compute capabilities offered by GPUs, and adoption of open-source philosophy by the researchers and industry. Deep neural networks can be decomposed into a series of different operators. MIOpen, AMD's open-source deep learning primitives library for GPUs, provides highly optimized implementations of such operators, shielding researchers from internal implementation details and hence, accelerating the time to discovery. This paper introduces MIOpen and provides details about the internal workings of the library and supported features. MIOpen innovates on several fronts, such as implementing fusion to optimize for memory bandwidth and GPU launch overheads, providing an auto-tuning infrastructure to overcome the large design space of problem configurations, and implementing different algorithms to optimize convolutions for different filter and input sizes. MIOpen is one of the first libraries to publicly support the bfloat16 data-type for convolutions, allowing efficient training at lower precision without the loss of accuracy.

Model compression has emerged as an important area of research for deploying deep learning models on Internet-of-Things (IoT). However, for extremely memory-constrained scenarios, even the compressed models cannot fit within the memory of a single device and, as a result, must be distributed across multiple devices. This leads to a distributed inference paradigm in which memory and communication costs represent a major bottleneck. Yet, existing model compression techniques are not communication-aware. Therefore, we propose Network of Neural Networks (NoNN), a new distributed IoT learning paradigm that compresses a large pretrained ‘teacher’ deep network into several disjoint and highly-compressed ‘student’ modules, without loss of accuracy. Moreover, we propose a network science-based knowledge partitioning algorithm for the teacher model, and then train individual students on the resulting disjoint partitions. Extensive experimentation on five image classification datasets, for user-defined memory/performance budgets, show that NoNN achieves higher accuracy than several baselines and similar accuracy as the teacher model, while using minimal communication among students. Finally, as a case study, we deploy the proposed model for CIFAR-10 dataset on edge devices and demonstrate significant improvements in memory footprint (up to 24×), performance (up to 12×), and energy per node (up to 14×) compared to the large teacher model. We further show that for distributed inference on multiple edge devices, our proposed NoNN model results in up to 33× reduction in total latency w.r.t. a state-of-the-art model compression baseline.

FPGAs have been proven to be powerful computational accelerators across many types of workloads. The mainstream programming approach is high level synthesis (HLS), which maps high-level languages (e.g. C+ #pragmas) to hardware. Unfortunately, HLS leaves a significant programmability gap in terms of reconfigurability, customization and versatility: Although HLS compilation is fast, the downstream physical design takes hours to days; FPGA reconfiguration time limits the time-multiplexing ability of hardware, and tools do not reason about cross-workload flexibility. Overlay architectures mitigate the above by mapping a programmable design (e.g. CPU, GPU, etc.) on top of FPGAs. However, the abstraction gap between overlay and FPGA leads to low efficiency/utilization. Our essential idea is to develop a hardware generation framework targeting a highly-customizable overlay, so that the abstraction gap can be lowered by tuning the design instance to applications of interest. We leverage and extend prior work on customizable spatial architectures, SoC generation, accelerator compilers, and design space explorers to create an end-to-end FPGA acceleration system. Our novel techniques address inefficient networks between on-chip memories and processing elements, as well as improving DSE by reducing the amount of recompilation required. Our framework, OverGen, is highly competitive with fixed-function HLS-based designs, even though the generated designs are programmable with fast reconfiguration. We compared to a state-of-the-art DSE-based HLS framework, AutoDSE. Without kernel-tuning for AutoDSE, OverGen gets 1.2$\times$ geomean performance, and even with manual kernel-tuning for the baseline, OverGen still gets 0.55$\times$ geomean performance--all while providing runtime flexibility across workloads.

Double-precision Dual Mode Logic carry-save multiplier

The gas sealing performance of electronic sphygmomanometer is an important index of its quality control. At present, the gas leak detection of sphygmomanometer is mainly by manual, which has disadvantages of low efficiency and precision, huge impact of human factors and so on. An automatic and high precision gas sealing performance inspection module is proposed in the paper, which solves the problems of pressure calibration and gas leak detection of sphygmomanometer products. The paper also introduces the principle and implementation of system project. The module is designed by STC12C5A single-chip, KPM DC air pump and the pressure sensor of E8CC, which has advantages of high precision, high efficiency, low cost, and flexible operation etc.

Micro‐expression recognition (MER) is a technology that infers emotions or intentions by analyzing subtle changes in facial expressions. It is often used to identify deception or assist interpersonal communication and holds significant value. Currently, MER technology is advancing rapidly; however, several challenges remain. To address the insufficient capture of local features and high computational complexity in MER, this paper proposes a novel lightweight network architecture. We introduce a Hierarchical Interactive Multi‐scale Pyramid Network (HIM‐PyraNet) that identifies key facial muscle movement regions while considering inherent spatial relationships between facial landmarks, differing from most existing studies using self‐attention mechanisms. HIM‐PyraNet comprises two main components: a Cross‐Region Interaction Attention (CRIA) module focusing on local temporal features and a Multi‐scale Feature Pyramid Fusion (MFPF) module integrating local and global semantics. Specifically, the face is divided into four distinct regions: left eye, right eye, left lip, and right lip. The CRIA module captures local micro‐muscle movements with region‐specific self‐attention, while the MFPF module learns interactions between eye and lip regions. This strategy effectively reduces the processing area for facial MER, successfully builds facial regional collaboration, and retains the local detailed features of expressions while reducing computational parameters. Experiments on SAMM, CASME II, and SMIC datasets show that with only 0.25M parameters, our model achieves 85.31% average recognition accuracy and 75.3 frames per second (FPS) inference speed. Compared with existing methods, this architecture demonstrates higher accuracy with a low parameter count, providing an innovative solution for real‐time micro‐expression analysis on edge devices.

Deep learning is finding its way into high energy physics by replacing traditional Monte Carlo simulations. However, deep learning still requires an excessive amount of computational resources. A promising approach to make deep learning more efficient is to quantize the parameters of the neural networks to reduced precision. Reduced precision computing is extensively used in modern deep learning and results to lower execution inference time, smaller memory footprint and less memory bandwidth. In this paper we analyse the effects of low precision inference on a complex deep generative adversarial network model. The use case which we are addressing is calorimeter detector simulations of subatomic particle interactions in accelerator based high energy physics. We employ the novel Intel low precision optimization tool (iLoT) for quantization and compare the results to the quantized model from TensorFlow Lite. In the performance benchmark we gain a speed-up of 1.73x on Intel hardware for the quantized iLoT model compared to the initial, not quantized, model. With different physics-inspired self-developed metrics, we validate that the quantized iLoT model shows a lower loss of physical accuracy in comparison to the TensorFlow Lite model.

Performing a motor task depends on the level of performance stabilization and movement control, and both aspects of motor behavior are related to motor learning (retention and transfer) and adaptation (predictable and unpredictable perturbations). Yet few studies have further investigated the underlying dynamics that may elicit these benefits. In this study, we investigated the effects of two levels of performance stabilization on motor performance and control while learning to intercept a virtual moving target. We randomly divided 40 participants of both sexes (Mage = 26.02 years, SD = 2.02) into a Stabilization Group (SG) and a Superstabilization Group (SSG). We considered the performance stabilized when a moving target was intercepted three times in a row and superstabilized when the same criterion was repeated six times. We analyzed outcome variables related to performance accuracy (absolute spatial error) and variability(coefficient of variation) and motor control (relative time to peak velocity-tPV% and its coefficient of variation) on both the first and last blocks of practice trials. Both groups showed comparable increases in performance accuracy from the first to the last block (p = .001, ηp2 = 1.00), but SSG presented higher variability than SG (p = .05, ηp2 = .70). Concerning motor control, both groups started the experiment with low tPV% and finished with comparably high tPV% and variability. Thus, although practicing two levels of performance stabilization led to similar performance accuracy and movement control, superstabilization resulted in higher performance variability with no loss of accuracy. Enhanced stabilization may increase the ability to adapt to environmental changes, but more research is needed to demonstrate this. These findings add to an understanding of the relationship between levels of performance stabilization and performance variability and may have implications for professional interventions (e.g. sports, rehabilitation) in considering the benefits of practice beyond performance stabilization.

Two calculation methods for iron-loss estimation of rotating machines are investigated. One is based on the conventional three-term expression. In this case, the losses are calculated from the time variation in the flux density obtained by the finite element analysis, which approximates the stator and rotor cores as solid magnetic materials without conductivity. The other is based on the 3-D eddy current analysis in the electrical steel sheet. In this case, the excess loss is calculated with a simple approximation. It is clarified that both methods can estimate the no-load iron loss in the similar accuracy and that the method based on the eddy-current analysis is suitable for the estimation of high-order harmonic iron losses.