Systematic approaches to testing embedded analogue circuit functions

Fault detection and diagnosis are critical challenges in Very Large Scale Integration (VLSI) circuits, where even minor defects can cause significant performance degradation or system failure. Traditional fault detection methods often struggle with scalability and real-time analysis as circuits grow increasingly complex. This paper proposes an AI-augmented framework that leverages machine learning algorithms and neural networks to enhance the fault detection process in VLSI circuits. The proposed model not only identifies and classifies faults with high accuracy but also provides root-cause diagnostics, significantly reducing testing time and maintenance costs. Simulation results demonstrate the effectiveness of the AI-based approach in comparison with conventional techniques, showcasing improved fault coverage, faster detection, and scalability for modern chip designs. This study serves as a step toward the integration of intelligent diagnostics into chip manufacturing, paving the way for more robust and self-healing electronic systems.

During the development of a VLSI (Very Large Scale Integration) circuits; their internal stress due to packaging combined with local self heating becomes serious and may result in large performance variation, circuit malfunction and even chip cracking. Surface peaks thermal detection is necessary in large VLSI circuits. This paper presents a VLSI circuit thermal stress monitoring approach using surface peak thermal detector algorithm and GDS (Gradient Direction Sensors) method. The design of surface peak thermal detector algorithm (SPTDA) with flexible modular-based architecture will be presented. Several approaches were implemented to achieve a better performance for the SPTDA algorithm operation. A parallel processing strategy is used to minimize computational delay. Furthermore, a hardware-efficient factoring approach for calculating tangent and division functions required by SPTDA algorithm is used to minimize silicon space in regards of their implementation. Description of the algorithm developed for the surface peaks thermal detection and the architecture implementation results are reported and compared with finite element method (FEM) temperature computations.

Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average.

Background and Objectives: High-level synthesis (HLS) is one of the substantial steps in designing VLSI digital circuits. The primary purpose of HLS is to minimize the digital units used in the system to improve their power, delay, and area.Methods: In the modified MFO algorithm presented in this paper, a hyperbolic spiral is chosen as the update mechanism of moths. Also, by presenting a new approach, a paramount issue involved in applying meta-heuristic methods for solving HLS problems of VLSI circuits has been disentangled.Results: By comparing the performance of the proposed method with Genetic algorithm (GA)-based method and particle swarm optimization (PSO)-based method for the synthesis of the digital filters, it is concluded that the proposed method has the higher ability in the HLS of data path in digital filters. The best improvement is 2.78% for the delay (latency), 6.51% for the occupied area of the chip and 6.93% in power consumption. Another feature of the proposed method is its high-speed in finding optimal solutions, in a manner which, more than 21.6% and 12.9% faster than the GA-based and PSO-based methods, respectively on average.Conclusion: The most important very large scale integration (VLSI) circuits are digital filters and transformers, which are widely used in audio and video processing, medical signal processing, and telecommunication systems. The complex, expansive, and discrete nature of design space in high-level synthesis problems has made them one of the most difficult problems in VLSI circuit design.

The interconnect temperature of very large scale integration (VLSI) circuits keeps rising due to self-heating and substrate temperature, which can increase the delay and power dissipation of interconnect wires. The thermal vias are regarded as a promising method to improve the temperature performance of VLSI circuits. In this paper, the extra thermal vias were used to decrease the delay and power dissipation of interconnect wires of VLSI circuits. Two analytical models were presented for interconnect temperature, delay and power dissipation with adding extra dummy thermal vias. The influence of the number of thermal vias on the delay and power dissipation of interconnect wires was analyzed and the optimal via separation distance was investigated. The experimental results show that the adding extra dummy thermal vias can reduce the interconnect average temperature, maximum temperature, delay and power dissipation. Moreover, this method is also suitable for clock signal wires with a large root mean square current.

Very large scale Integration (VLSI) was used to create hardware which initiates by the explanation of algorithm as well as employs computer program. In digital systems, multiplier and adder are the fundamental components in design of integrated circuit applications. High speed devices play an essential role in VLSI applications. Adder enhancement is used in miscellaneous application in new VLSI system like multiplier design, ALU and etc. An efficient adder circuit design is used to optimize various metrics. But, design complexity was not reduced by existing VLSI design. To handle such limitations, Deep Fully Connectedness Convolutional Broken Stick Regressive Brent-Kung Adder Enhancement (DFCCBSRBKAE) Technique is introduced in VLSI circuits. Input layer, two hidden layers as well as output layer comprises four layer of DFCCBSRBKAE Technique. The carry inputs are transferred to input layer. Input data is transferred to hidden layer 1. Broken-stick regression analysis is performed for pre-processing data. Next, pre-processed data is transferred to hidden layer 2. Carry generation and post-processing is carried out in hidden layer 2 and the output results are covered by the convolution. At last, outcomes were attained within output layer. This in turn helps to perform an efficient adder enhancement of digital multiplier with minimal power and time consumption. The performance of DFCCBSRBKAE Technique is determined by power and time consumption. DFCCBSRBKAE Technique reduces the area, speed, and delay and power consumption of adder enhancement compared with conventional methods.

A very large scale integrated-circuit (VLSI) floorplan can be represented in an ordered tree (O-tree), and therefore the VLSI floorplan optimization problem can be transformed into an O-tree permutation problem. This paper presents a new greedy O-tree permutation algorithm and applies it to the VLSI floorplan optimization problem.

With the rapid advancement of portable and battery-operated electronic devices, power consumption has become a critical constraint in Very Large Scale Integration (VLSI) circuit design. This paper provides an overview of the key low-power design strategies employed to optimize VLSI circuits. Techniques such as voltage scaling, clock gating, power gating, and transistor-level optimizations are discussed to address leakage and dynamic power dissipation. The study highlights trade-offs between power, performance, and area, and presents recent methodologies to achieve efficient low-power VLSI design. The insights offered aim to guide designers in developing energy-efficient integrated circuits while maintaining performance benchmarks.

Graph partitioning applied to the logic testing of combinational circuits

Capacitance extraction for interconnect parasitics modeling is the basis of accurate circuit simulation and physical verification for quality integrated circuit (IC) design. Due to its scalability and reliability, the floating random walk (FRW) based solver has been widely used for the capacitance extraction. In this paper, the recently developed techniques on distributed parallel FRW solver and for handling complex floating metals are presented. With them, the efficiency and accuracy of capacitance extraction/simulation for very large-scale integration (VLSI) circuit design are remarkably improved.

Spike Timing Dependent Plasticity (STDP) is a time-based synaptic plasticity rule that has generated significant interest in the area of neuromorphic engineering and Very Large Scale Integration (VLSI) circuit design. During the last decade, STDP and STDP-like learning mechanisms have shown promising solutions for various real world applications, ranging from pattern recognition to robotics. This paper presents a novel analog VLSI model for STDP that possesses advantages compared to previously published VLSI STDP designs. The presented STDP circuit is capable of reproducing the outcomes of several well known experiments using various plasticity rules inducing STDP protocols that utilise pairs, triplets, and quadruplets of spike patterns. When the circuit is compared to state-of-the-art VLSI STDP circuits, it shows a compact and symmetric design that makes the proposed circuit a powerful component for use in designing STDP or time-based Hebbian learning experiments and applications.

The lack of multi-scale empirical measurements (e.g., recording simultaneously from neurons, muscles, whole body, etc.) complicates understanding of sensorimotor function in humans. This is particularly true for the understanding of development during childhood, which requires evaluation of measurements over many years. We have developed a synthetic platform for emulating multi-scale activity of the vertebrate sensorimotor system. Our design benefits from Very Large Scale Integrated-circuit (VLSI) technology to provide considerable scalability and high-speed, as much as 365× faster than real-time. An essential component of our design is the proprioceptive sensor, or muscle spindle. Here we demonstrate an accurate and extremely fast emulation of a muscle spindle and its spiking afferents, which are computationally expensive but fundamental for reflex functions. We implemented a well-known rate-based model of the spindle (Mileusnic et al., 2006) and a simplified spiking sensory neuron model using the Izhikevich approximation to the Hodgkin–Huxley model. The resulting behavior of our afferent sensory system is qualitatively compatible with classic cat soleus recording (Crowe and Matthews, 1964b; Matthews, 1964, 1972). Our results suggest that this simplified structure of the spindle and afferent neuron is sufficient to produce physiologically-realistic behavior. The VLSI technology allows us to accelerate this behavior beyond 365× real-time. Our goal is to use this testbed for predicting years of disease progression with only a few days of emulation. This is the first hardware emulation of the spindle afferent system, and it may have application not only for emulation of human health and disease, but also for the construction of compliant neuromorphic robotic systems.

Developing computationally efficient processing techniques for massive volumes of hyperspectral data is critical for space-based Earth science and planetary exploration (see for example, (Plaza & Chang, 2008), (Henderson & Lewis, 1998) and the references therein). With the availability of remotely sensed data from different sensors of various platforms with a wide range of spatiotemporal, radiometric and spectral resolutions has made remote sensing as, perhaps, the best source of data for large scale applications and study. Applications of Remote Sensing (RS) in hydrological modelling, watershed mapping, energy and water flux estimation, fractional vegetation cover, impervious surface area mapping, urban modelling and drought predictions based on soil water index derived from remotelysensed data have been reported (Melesse et al., 2007). Also, many RS imaging applications require a response in (near) real time in areas such as target detection for military and homeland defence/security purposes, and risk prevention and response. Hyperspectral imaging is a new technique in remote sensing that generates images with hundreds of spectral bands, at different wavelength channels, for the same area on the surface of the Earth. Although in recent years several efforts have been directed toward the incorporation of parallel and distributed computing in hyperspectral image analysis, there are no standardized architectures or Very Large Scale Integration (VLSI) circuits for this purpose in remote sensing applications. Additionally, although the existing theory offers a manifold of statistical and descriptive regularization techniques for image enhancement/reconstruction, in many RS application areas there also remain some unsolved crucial theoretical and processing problems related to the computational cost due to the recently developed complex techniques (Melesse et al., 2007), (Shkvarko, 2010), (Yang et al., 2001). These descriptive-regularization techniques are associated with the unknown statistics of random perturbations of the signals in turbulent medium, imperfect array calibration, finite dimensionality of measurements, multiplicative signal-dependent speckle noise, uncontrolled antenna vibrations and random carrier trajectory deviations in the case of Synthetic Aperture Radar (SAR) systems (Henderson & Lewis, 1998), (Barrett & Myers, 2004). Furthermore, these techniques are not suitable for

As the integration scale of very large-scale integration (VLSI) circuits increases, it is becoming increasingly difficult to design long and complex process flows because there is a great amount of knowledge required in VLSI process technology. To assist in process-flow design, a rule-based validation system has been developed. This system checks designed process flows by using process knowledge related to contamination, cleaning methods, and the various constraints between the wafer structure and the process or equipment. It can point out error conditions that lead to such destructive results as contamination of the process equipment. The system applies process knowledge, expressed as if/then rules, to the process conditions and to macroscopic wafer structures derived from rule-based simulation. Due to the complexity of VLSI multilayered structures, information related to wafer structure is very important. This information can be obtained by rule-based simulation of such various macroscopic attributes of wafer structure as substance, contamination, and layer thickness. The validation system can precisely check various process flows and substantially improve the efficiency and quality of process-flow design. >

Due to the rapid advancements in semiconductor production, increasing design complexity, and the need for gigahertz operating frequencies, designing VLSI circuits digitally presents several obstacles. Keeping power dissipation within reasonable bounds is one of the main issues designers face. The necessity for portable electronics, the shrinking transistor sizes, and the growing number of devices per chip all contribute to rising power consumption. The design and verification of very large-scale integration (VLSI) circuits depend heavily on this issue. Therefore, minimizing power dissipation throughout the design phase is crucial and requires precise power dissipation estimation. This enables the prevention of expensive and highly complex redesigns that might emerge due to violation of the power constraint. This paper presents a power estimation technique based on the backpropagation neural networks for estimating power consumption of the combinational and sequential circuits. In the proposed method, mean square error and regression analysis are used for measuring the deviations between the actual power and estimated power obtained by SPICE/Monte Carlo simulation. The deviations from the ideal power estimator using BPNN are found to be approximately 0.77% for NAND-based and 1.04% for NOR-based combinational circuits, and around 0.01% for sequential circuits. The MSE for NAND and NOR combinational circuits is 0.88751 and 1.08402, respectively, while for sequential circuits, it is approximately 6.254 × 10−5. These results demonstrate that the BPNN-based method provides highly accurate power estimation.