Systolic algorithm for polynomial interpolation and related problems

Lin, Chung and Han introduced in 2014 the LCH-basis in order to derive FFT-based multipoint evaluation and interpolation algorithms with respect to this polynomial basis. Considering an affine space of n = 2j points, their algorithms require O(n · log2 n) operations in F2r. The LCH-basis has then been extended over finite fields of characteristic p by Lin et al. in 2016 and an n-point evaluation algorithm has been derived for n = pj with complexity O(n · logp n · p). However, the problem of interpolating polynomials represented in such a basis over FPr has not been addressed.

The problem of polynomial interpolation is to reconstruct a polynomial based on its valuations on a set of inputs I. We consider the problem over $\mathbb{Z}_m$ when m is composite. We ask the following question: Given $I \subseteq \mathbb{Z}_m$, how many evaluations of a polynomial at points in I are required to compute its value at every point in I? Surprisingly for composite m, this number can vary exponentially between $\log |I|$ and $|I|$, in contrast to the prime case where $|I|$ evaluations are necessary. While we show this minimization problem to be NP-hard, we give an efficient algorithm of query complexity within a factor t of the optimum, where t is the number of prime factors of m. We use our interpolation algorithm to design algorithms for zero testing and distributional learning of polynomials over $\mathbb{Z}_m$. In some cases, we get an exponential improvement over known algorithms in query complexity and running time. Our main technical contribution is the notion of an interpolating set for I which is a subset S of I such that a polynomial which is 0 over S must be 0 at every point in I. Any interpolation algorithm needs to query an interpolating set for I. Our query-efficient algorithms are obtained by constructing interpolating sets whose size is close to optimal.

Efficient implementation of global computations on a linear array of processors is complicated due to the small communication bandwidth and the large communication diameter of the array. This paper presents efficient parallel techniques for partitioning, movement, and reduction of data on linear arrays. Also, efficient data structures are used to enable fast sequential access of query points within each processor. This combination of serial and parallel techniques is used to derive an optimal parallel algorithm for computing the convex hull of each connected region in an n×n image. The algorithm takes O(n 2/p) time on a linear array with p processors, where 1≤p≤n/log n. This result is processor-time optimal since an optimal sequential algorithm takes O(n 2) to solve the problem. Thus, a linear array with n/log n processors can solve the above problem in O(n log n) time. In comparison, a two dimensional mesh-connected array of processors can solve this problem in O(n) time using n 2 processors. The processor-time product for the mesh is O(n 3), which is not optimal.KeywordsConvex HullExtreme PointLinear ArrayLocal MemoryQuery PointThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Parallel sorting with cooperating heaps in a linear array of processors

We show that there is a set of pointsp 1,p 2,...,p n such that any arithmetic circuit of depthd for polynomial evaluation (or interpolation) at these points has size $$\Omega \left( {\frac{{n\log n}}{{\log (2 + d/\log n}}} \right).$$ Moreover, for circuits of sub-logarithmic depthd, we obtain a lower bound of Ω(dn 1+1/d ) on its size.

We present a unified framework for most of the known and a few new evaluation algorithms for multivariate polynomials expressed in a wide variety of bases including the Bernstein-Bézier, multinomial (or Taylor), Lagrange and Newton bases. This unification is achieved by considering evaluation algorithms for multivariate polynomials expressed in terms of L-bases, a class of bases that include the Bernstein-Bézier, multinomial, and a rich subclass of Lagrange and Newton bases. All of the known evaluation algorithms can be generated either by considering up recursive evaluation algorithms for L-bases or by examining change of basis algorithms for L-bases. For polynomials of degree n n in s s variables, the class of up recursive evaluation algorithms includes a parallel up recurrence algorithm with computational complexity O ( n s + 1 ) O(n^{s+1}) , a nested multiplication algorithm with computational complexity O ( n s log ⁡ n ) O(n^s \log n) and a ladder recurrence algorithm with computational complexity O ( n s ) O(n^s) . These algorithms also generate a new generalization of the Aitken-Neville algorithm for evaluation of multivariate polynomials expressed in terms of Lagrange L-bases. The second class of algorithms, based on certain change of basis algorithms between L-bases, include a nested multiplication algorithm with computational complexity O ( n s ) O(n^s) , a divided difference algorithm, a forward difference algorithm, and a Lagrange evaluation algorithm with computational complexities O ( n s ) O(n^s) , O ( n s ) O(n^s) and O ( n ) O(n) per point respectively for the evaluation of multivariate polynomials at several points.

This paper shows how a real-time simulator of moving pictures compression algorithms can be rapidly assembled using a basic building block, here called MOVIE (MOdule for Video Experimentation). The internal architecture of the MOVIE VLSI chip can be compared to a small systolic machine made of a 32-bit I/O processor, a reduced linear array of 16-bit computation processors and data video input/output mechanisms. Externally, the chip is provided with four 16-bit bidirectional data ports and three 16-bit bidirectional data video port. Several MOVIE chips can be easily clustered to allow the size of the linear array of computation processors to be increased. The MOVIE chip is fully programmable in a high level language in order to make program developments easier.

The authors describe a hardware architecture called Ringtree for 2D geometry generation and processing such as image processing (noise suppression, notch elimination and contour extraction), graphics processing (polygon filing and multiwindowing with nonrectangular windows), and VLSI layout verification (design-rule checking). Ringtree consists of a ring memory which is a special rotating frame buffer, an edge painting tree (EPT), which is a polygon rasterizing hardware, and a linear processor array (LPA). The LPA executes a set of basic operations applicable for bit map data manipulation while the EPT generates the bit map data from a set of scanline commands received from host processor. VLSI implementation issues are also discussed for practical display screen size of 1024*1024 pixels, utilizing the Super Tree concept of J. Poulton et al. (1985) for realizing the whole system using identical VLSI chips. >

We study the problem of generating the monomials of a black box polynomial in the context of enumeration complexity. We present three new randomized algorithms for restricted classes of polynomials with a polynomial or incremental delay, and the same global running time as the classical ones. We introduce TotalBPP, IncBPP and DelayBPP, which are probabilistic counterparts of the most common classes for enumeration problems. Our interpolation algorithms are applied to algebraic representations of several combinatorial enumeration problems, which are so proved to belong to the introduced complexity classes. In particular, the spanning hypertrees of a 3-uniform hypergraph can be enumerated with a polynomial delay. Finally, we study polynomials given by circuits and prove that we can derandomize the interpolation algorithms on classes of bounded-depth circuits. We also prove the hardness of some problems on polynomials of low degree and small circuit complexity, which suggests that our good interpolation algorithm for multilinear polynomials cannot be generalized to degree 2 polynomials. This article is an improved and extended version of Strozecki (Mathematical Foundations of Computer Science, pp. 629---640, 2010) and of the third chapter of the author's Ph.D. Thesis (Strozecki, Ph.D. Thesis, 2010).

Lower bounds for two call control problems

The paper presents a parallel architecture for a pel-recursive motion estimation algorithm. It is a linear array of processors, each consisting of an initialization part, a data-routing part and an updating part. The initializing part performs a prediction of the motion vector. The routing parts constitute a routing path along which previous-frame data is routed from processors that store to processors that request such data. A clocked version of the router is presented with some detail. The updating part calculates an update to the predicted motion vector. The architecture proposed is derived in a systematic way and is parameterized w.r.t. certain window sizes. It is thus completely different from the few existing pel-recursive motion estimation architectures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Updating URV decompositions in parallel

The problem of bivariate interpolation in algebraic soft decision decoding of Reed-Solomon codes is considered. Re-encoding transformation for the case of layered interpolation algorithm is derived. A novel hybrid interpolation algorithm based on layered, Lee-O'Sullivan and Kotter algorithms is proposed. The proposed algorithm demonstrates considerable complexity reduction compared to the case of iterative interpolation algorithm.

The papers [18], [9], [29], and [28] combine the techniques of the Fast Multipole Method of [15], [8] with the transformations of matrix structures, traced back to [19]. The resulting numerically stable algorithms approximate the solutions of Toeplitz, Hankel, Toeplitz-like, and Hankel-like linear systems of equations in nearly linear arithmetic time, versus the classical cubic time and the quadratic time of the previous advanced algorithms. We extend this progress to decrease the arithmetic time of the known numerical algorithms from quadratic to nearly linear for computations with matrices that have structure of Cauchy or Vandermonde type and for the evaluation and interpolation of polynomials and rational functions. We detail and analyze the new algorithms, and in [21] we extend them further.

New telephone features and their increasingly complex interactions with one another requires better performance from Telecommunication Switching systems. Since call processing is the most computationally expensive task in a switch, multi-processor systems are being considered for the call processing cores of many commercial switch architectures. In this thesis, the design criteria for such a call processing system have been generated and analyzed. A new approach, the heterogeneous linear pipelined array is proposed and compared with a common load sharing architecture. The linear pipelined array has been simulated using a detailed Verilog Hardware Description Language model, to further verify its suitability for call processing applications. Several fixed assignment schemes and three simple heuristic assignment schemes have been simulated and the resulting throughput and processor utilizations has been studied. A semi-static approach has been tested, where an optimal schedule is determined based on the relative quantities of calls in specific states. The performance of the array for the call processing task is shown, for a variety of cases, to be dependent on the degree of load balancing which can be achieved in the array and the extent to which processing bottlenecks can be avoided. The results for the semi-static schedules are significantly better than for the fixed schemes. (Abstract shortened by UMI.)