Task management in MPSoCs

The design of efficient multiprocessor systems on chip (MPSoC) is a daunting challenge. This challenge is driven by the increasing demand in achieving high performance, low power, and reconfigurable applications onto the same platform. As a consequence, there is an emerging need for fast, and efficient design space exploration, while providing abstract models for a wide range of applications, and types of processing units (PUs). Therefore, this paper proposes a framework for a fast MPSoC generation with joint task and core mapping with the objective of minimizing the average power consumption. The proposed framework considers the static, dynamic, reconfiguration and communication power components. A tool for high level MPSoC task and core mapping (MPMAP) is built based on the proposed framework. MPMAP provides a flexible XML interface that provides a high level description of the different PU architectures, and different applications scenarios. Additionally, the paper presents a case study of real-life applications that can be adopted in future heterogeneous wireless systems.

As one of the most significant parts in the development of the next generation infrared detection system, the infrared signal processing system requires the ability of real-time processing and high speed data transmission. A newly developed real-time signal processing system for infrared detecting based on the heterogeneous multiprocessor system on chip (MPSoC) is proposed in this paper. The device follows the architecture of Xilinx Zynq platform, integrating a feature rich dual-core ARM and Xilinx FPGA in a single chip, built on the 28nm high-k metal gate process technology. According to our design, the FPGA fabric portion retains all the programmable flexibility to drive the infrared detector and acquire data from ADC, with registers parallel operations to implement hardware acceleration. Furthermore, the FPGA fabric is connected to the ARM centered processor unit through multiple high performance interfaces, confirming high bandwidth communication and high speed data transmission between the two portions. Finally, the dual core ARM takes charge of the infrared signal processing system in general. One of the CPUs controls separate hardware modules and maintains the GUI for user interaction. The other responds to the dedicated system commands and external interrupts to update system parameters simultaneously. The integration of ARM and FPGA provides levels of performance that two-chip solutions cannot match due to their limited I/O bandwidth, loose coupling and power budgets. Experiments show that the architecture of heterogeneous MPSoC enhances the efficiency of memory controller and increases the speed of data transmission, approaching the theoretical value of the interfaces bandwidth.

Multimedia embedded systems require high performance specific computation to process the large among of data that characterizes the multimedia domain at low energy consumption due to battery life. Different optimizations at different levels can considerably improve performance and energy consumption and, after that, the address generation becomes the new performance bottleneck. This paper shows a custom-configurable address generation unit design which extends an application specific instruction set processor (ASIP) to boost the address calculations, improving performance and reducing the energy consumption around 27%. The main innovation of our work resides in a new custom-configurable AGU design which can be automatically implemented and directly connected to the ASIP data-path. This AGU design has a fast interface which allows reading one address in only one cycle and one instruction, and calculates new values without stopping the processor. The presented design can easily be implemented in broad range of ASIPs.

The ever increasing performance gap between processors and memories is one of the biggest performance bottlenecks for computer systems. In this paper, we propose a task scheduling technique that schedules an application, modeled with a task graph, on a multiprocessor system-on chip (MPSoC) that contains a limited on-chip memory. The proposed scheduling technique explores the trade-off between executing tasks in a code-driven (i.e. executing parallel tasks) or data-driven (i.e. executing pipelined tasks) manner to minimize the run-time of the application. Our static scheduler identifies those task sequences in which it is useful to use a code-driven execution and those task sequences that benefit from a data-driven execution. We extend the proposed technique to consider prefetching when choosing a suitable task order. The technique is implemented using an integer linear programming framework. To evaluate the effectiveness of the technique, we use an application from the multimedia domain and a synthetic task graph that is used in related work. Our experimental results show that our scheduler is able to reduce the run-time of an MP3 decoder application by 8% compared to a commonly used heuristic scheduler.

In today's multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities and to achieve the 100 Gops/W energy efficiency target required for ambient intelligence applications. However, mapping abstract programming models onto tightly power-constrained hardware architectures imposes overheads which might seriously compromise performance and energy efficiency. The objective of this work is to perform a comparative analysis of message passing versus shared memory as programming models for single-chip multiprocessor platforms. Our analysis is carried out from a hardware-software viewpoint: we carefully tune hardware architectures and software libraries for each programming model. We analyze representative application kernels from the multimedia domain, and identify application-level parameters that heavily influence performance and energy efficiency. Then, we formulate guidelines for the selection of the most appropriate programming model and its architectural support

Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which design space exploration (DSE), system-level synthesis, application mapping, and system prototyping of MP-SoCs are highly automated. In this paper, we describe our first industrial deployment experiences with the Daedalus framework. Daedalus is currently being deployed in the early stages of the design of an image compression system for very high resolution cameras targeting medical appliances. In this context, we performed a DSE study with a JPEG encoder application, which exploits both task and data parallelism. This application was mapped onto a range of different MP-SoC architectures. We achieved a performance speed-up of up to 20x compared to a single processor system. In addition, the results show that the Daedalus high-level MP-SoC models accurately predict the overall system performance, i.e., the performance error is around 5%.

Fine-grained task models can exploit parallelism to achieve high performance for multiprocessor system-on-chip (MPSoC). However, fine-grained models face the issues of high-communication overhead and difficult scheduling decisions, and the two challenges are inter-dependent. To address the issues, this paper gives a full analysis of the fine-grained communication optimization technique and communication pipeline, from both time and topology perspectives, and proposes a static fine-grained communication-aware task scheduling (FCATS) approach, which integrates scheduling with communication pipeline for acyclic and cyclic applications based on the fine-grained Simulink model. The approach contains search-based scheduling with high-quality solutions utilizing genetic algorithm-integer linear programming (GA-ILP) and hybrid GA-heuristic scheduling with short solving time to meet different demands for users. The experimental results with both synthetic and real-life benchmarks on the 4/8/16-CPU platform demonstrate the efficiency of the approach on performance improvements compared to previous works.

In this paper, a hybrid scheduling and mapping approach to jointly optimize performance, lifetime reliability, energy consumption and temperature of heterogeneous multiprocessor systems on chip (MPSoCs), called “HYSTERY,” is proposed. Due to the growth of dynamic behavior in modern applications of embedded systems, along with necessity of performing complicated computations to jointly optimize the main design challenges of MPSoCs, we propose a hybrid scheduling approach in this paper. The proposed approach deals with the optimization of the mentioned design challenges at the design-time through solving an optimization problem and considering load balancing in task assignment. Moreover, at the runtime, the derived static solution is applied to the system and the design metrics monitored periodically and controlled, if required, to adapt the static scheduling decisions at the runtime. Several experiments with synthetic and real-life applications demonstrate that the proposed approach can effectively optimize the design challenges and manage dynamism of execution environment. In comparison with the uncontrolled runtime scheduling approach, HYSTERY shows 20% improvement in temperature averagely, which subsequently enhance lifetime reliability and power consumption. Furthermore, HYSTERY improves the main design parameters of MPSOCs about 21% in average compared to the existing scheduling approaches.

Modern embedded applications keep getting more complex, while battery-powered platforms still face strict energy limits. This makes it crucial to design energy-efficient task mapping strategies for Network-on-Chip (NoC)-based heterogeneous Multi-Processor System-on-Chip (MPSoCs). To address this, we present a novel discrete optimization technique called the Binary Chimp Optimization Algorithm (BChOA). It is built to cut energy use when mapping multiple application tasks onto heterogeneous MPSoC architectures. BChOA takes the population behavior from the original Chimp Optimization Algorithm (ChOA) and modifies it to work more effectively with binary problems. It employs a sigmoid-based method to handle the transition from continuous to discrete, enabling it to search through the space of possible task-to-core assignments more effectively. We tested the effectiveness of BChOA by comparing it to three popular optimization methods: Particle Swarm Optimization (PSO), Genetic Algorithm (GA), and Ant Colony Optimisation (ACO). We ran all of them on standard application benchmarks like VOPD, MPEG-4, MMS, MWD, and PIP. BChOA ultimately proved to be more energy-efficient across the board. On average, it used 7.73% less energy than GA, 4.50% less than PSO, and 1.71% less than ACO. We also examined where each of these methods excelled and where they fell short, all within the context of task mapping for NoC-based heterogeneous MPSoC systems.

Novel solutions are needed to fulfill the increasing demands of embedded systems, i.e. lowering the energy consumption, increasing the performance, reducing the development time and keeping the costs as low as possible. In addition, there exist several applications, which require runtime adaptations of the algorithms based on the connection to its environment. These challenges can be solved by using reconfigurable Multiprocessor Systems-on- Chip (MPSoCs), which can adapt the hardware as well as the software to the application requirements and therefore achieve a high computational efficiency as well as a high flexibility. However, the development, the programming and the operation of such flexible and heterogeneous systems is very complex as the many criteria (Performance, power consumption, costs, development time, runtime adaptations, etc.) open a huge design space. In this paper an overview of the challenges faced when developing runtime adaptive MPSoCs is given. Finally, for each challenge a survey of possible solutions are presented.

Summary form only given. Future automotive security systems will benefit from visual scene analysis based on a fusion of video, infrared, and radar images. Today we have already functions like lane departure warning and automatic cruise control (ACC) for pretty well defined driving environments, such as highways and primary roads. Recent research activities concentrate on more complex environments, such as city traffic with a wide variety of traffic participants moving in an unpredictable manner, e.g. bikes, pedestrians, children, and even animals, and under changing weather and lighting conditions. The ITRS semiconductor roadmap for microelectronics forecasts a continued doubling of transistor capacity per chip every 2 to 2.5 years enabling billion transistor ASIC designs in the near future. Multi processor system on chip (MPSoC) solutions with 8, 16 or even more standard RISC CPU cores, mega-bytes of fast (ns access latencies) on-chip SRAM memories, giga-byte per second interconnect buses or NoC (network on chip) meshes, high-speed serial I/Os and, last but not least, million gate equivalent dedicated hardware accelerator functions in eFPGA (embedded field programmable gate array) logic are becoming reality on a single silicon substrate. Examples of current research projects shall illustrate our perception on how this tremendous increase in functionality and computational performance per chip area may impact automotive control unit (ACU) architectures for driver assistance applications. The AutoVision processor is a dynamically MPSoC prototype where video-specific pixel processing engines are on-the-fly loaded or exchanged without interrupting regular system operations. For the time being, pixel processing engines cover functions such as object edge detection or luminance segmentation, and are implemented as dedicated hardware accelerators to ensure real-time frame processing capabilities of the AutoVision processor. Dynamic replacement of processing engines ensures an automatic and area efficient adaptation to various driving conditions. Segmented objects are, in a subsequent step, characterized by means of standard MPEG-7 descriptors and entered as search criteria into traffic scene analysis databases. Goal is to obtain a clean distinction between passenger cars, trucks, and big rectangular traffic signs, and to identify pedestrians or bikers in complex traffic situations. The AutoVision processor project is supported by the German Research Foundation (DFG) in the special emphasis research programme reconfigurable computing.

Nowadays, aggressive scaling in integrated circuits brings out new challenges such as increase in power density, temperature, and process variation in designing Multiprocessor Systems-on-Chip (MPSoC) employed in embedded systems. While most of the previous works attempt to mitigate the process variation effects in system design level, the eventual design still is inefficient and suffers from the variability of frequency and leakage power of processors in a MPSoC. In this paper, we formulate a MILP problem for variation-aware task assignment and scheduling to optimize power consumption while meeting the real-time constraints. To capture stochastic behavior of process variation, we employ chance-constrained programming technique to turn the problem into a corresponding stochastic optimization one that can be solved by typical solvers. Extensive experiments using E3S benchmarks have been carried out and the obtained results of the proposed method evince improvements compared to the baseline method in terms of performance-yield and run-time.

The various theories of model based refinement that have arisen over the years offer powerful methods of transforming abstract formal models into (what are ultimately) implementations, with a high degree of assurance that suitable properties of the abstract model have been preserved. Formal model based refinement has had considerable success in selected critical projects such as the Meteor Project for the Paris Metro and a number of smartcard based developments such as the Mondex Purse and the Javacard. However, refinement is very demanding as regards the precise relationship between abstract models and their more concrete counterparts, and these aspects can inhibit its use, or at least undermine its connection to system requirements

The heterogeneous multicore system integrated with FPGA is a kind of Multi-Processor Systems-on-Chip(MPSoC) that can achieve both efficiency and flexibility. FPGA uses hardware resource instead of instruction sets to process tasks. The resource on FPGA is limited which should be considered when scheduling tasks. We propose a static task scheduling algorithm targeting this kind of system. The aim is to minimize the executing time of an application as well as considering FPGA resource limit. In our genetic algorithm-based method, a chromosome consists of computing units where tasks are assigned. When generating the initial population, some tasks are assigned to FPGA, considering FPGA resource limit. We have modified the crossover operator and mutation operator to ensure that the FPGA resource used implied in chromosomes will not exceed the FPGA resource limit. Task scheduling is completed in the chromosome evaluation stage. Through the genetic algorithm, the improved task assignment and schedule sequence are obtained. The experiments on random graph applications and two real-world applications show that our method has achieved better performance than existing works.

The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in the amount of data they manipulate. The memory bottleneck is even more important for multiprocessor-system-on-a-chip (MPSoC) architectures due to the high cost of off-chip memory accesses in terms of both energy and performance. As a result, reducing the memory-space occupancy of embedded applications is very important and will be even more important in the next decade. While it is true that the on-chip memory capacity of embedded systems is continuously increasing, the increases in the complexity of embedded applications and the sizes of the data sets they process are far greater. Motivated by this observation, this paper presents and evaluates a compiler-driven approach to data compression for reducing memory-space occupancy. Our goal is to study how automated compiler support can help in deciding the set of data elements to compress/decompress and the points during execution at which these compressions/decompressions should be performed. We first study this problem in the context of single-core systems and then extend it to MPSoCs where we schedule compressions and decompressions intelligently such that they do not conflict with application execution as much as possible. Particularly, in MPSoCs, one needs to decide which processors should participate in the compression and decompression activities at any given point during the course of execution. We propose both static and dynamic algorithms for this purpose. In the static scheme, the processors are divided into two groups: those performing compression/decompression and those executing the application, and this grouping is maintained throughout the execution of the application. In the dynamic scheme, on the other hand, the execution starts with some grouping but this grouping can change during the course of execution, depending on the dynamic variations in the data access pattern. Our experimental results show that, in a single-core system, the proposed approach reduces maximum memory occupancy by 47.9% and average memory occupancy by 48.3% when averaged over all the benchmarks. Our results also indicate that, in an MPSoC, the average energy saving is 12.7% when all eight benchmarks are considered. While compressions and decompressions and related bookkeeping activities take extra cycles and memory space and consume additional energy, we found that the improvements they bring from the memory space, execution cycles, and energy perspectives are much higher than these overheads.