Techniques for Improving Performance of Hybrid Snooping Cache Protocols

Although directory-based write-invalidate cache coherence protocols have a potential to improve the performance of large-scale multiprocessors, coherence misses limit the processor utilization. Therefore, so called competitive-update protocols — hybrid protocols between write-invalidate and write-update — have been considered as a means to reduce the coherence miss rate and have been shown to be a better coherence policy for a wide range of applications. Unfortunately such protocols may cause high traffic peeks for applications with extensive use of migratory objects. These traffic peeks can offset the performance gain of a reduced miss rate if the network bandwidth is not sufficient.We propose in this study to extend a competitive-update protocol with a previously published adaptive mechanism that can dynamically detect migratory objects and reduce the coherence traffic they cause. Detailed architectural simulations based on five scientific and engineering applications show that this adaptive protocol can outperform a write-invalidate protocol by reducing the miss rate and bandwidth need by as much as 71% and 26%, respectively.

Wireless Sensor Network (WSN) frameworks assemble an entryway that gives remote availability back to the wired world and conveyed node. Finding appropriate routes in a network is the main objective considered for WSN. Many routing protocols have been developed for selecting efficient and reliable paths but it is strenuous to tell which protocol acts better for various network frameworks. Simulations are performed in WSN by using different software or simulators for analyzing the routing protocols. In this research work, extensive performance analysis has been done on three types of routing protocols. Performance evaluation on Proactive routing protocol (DSDV and OLSR), Reactive routing protocol (AODV and AOMDV) and Hybrid protocol (ZRP) with a changeable network environment have been done in this paper. The performance measuring is analyzed on the basis of throughput, end-to-end delay, normalized routing load, average jitter and transmit energy consumption depends by changing the number of nodes and pause time. Five different performance parameters have made this work unique as well as help to the proper understanding of the working procedure of three categories routing protocols. The performance has been calculated with the help of network simulator NS-2.35.

Snoopy protocols represent a very popular class of hardware cache coherence solutions, especially suitable for bus-based, shared memory multiprocessors. It is not firmly established which of the two main approaches (write-invalidate or write-broadcast) is superior over the wide range of applications. An enhancement of write-invalidate protocols is proposed, introducing the word invalidation capability. Simulations with a synthetic workload model were performed, in order to analyze its behavior, and to compare it with the best representatives of write-invalidate and write-broadcast protocols. Performance evaluation was done for simulated workloads with a lower and a higher degree of sharing, as well. An attempt is made to model some effects of process switching and migration. Finally, some implications of using a more advanced bus technology on snoopy protocols performance is discussed. >

The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to be slow, compared to the ever-increasing speeds of processors. Thus, any scalable architecture must rely on techniques that can cope with the large latency of memory accesses to reduce/hide/tolerate remote-memory-access latencies.

Article Free Access Share on The impact of architectural trends on operating system performance Authors: M. Rosenblum Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , E. Bugnion Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , S. A. Herrod Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , E. Witchel Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile , A. Gupta Computer Systems Laboratory, Stanford University, Stanford CA Computer Systems Laboratory, Stanford University, Stanford CAView Profile Authors Info & Claims SOSP '95: Proceedings of the fifteenth ACM symposium on Operating systems principlesDecember 1995Pages 285–298https://doi.org/10.1145/224056.224078Published:03 December 1995Publication History 188citation2,012DownloadsMetricsTotal Citations188Total Downloads2,012Last 12 Months295Last 6 weeks50 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

One of the most important concepts that must be understood by students of parallel computer architecture is cache coherence. Processors may change the value of shared variables by writing them in their private caches. These changes must be propagated to the far reaches of the system so that writes to each location are seen in the same sequence throughout the system. Of course, this can be achieved by various protocols, depending on the size of the system and the workload. Students can gain an in-depth understanding of these protocols by simulating them. Our approach is to provide students with an abstract simulator, which can be specialized through inheritance in C++ to model many different protocols. The protocols can be divided into bus based and directory based. Either of these can be invalidation or update. Hybrid and adaptive protocols can also be simulated. Among the protocols covered are MSI, MESI, MOESI, Firefly, Dragon, and a simplified SCI protocol. It would be easy to add additional protocols by subclassing appropriate classes.

article Free Access Share on A program-driven simulation model of an MIMD multiprocessor Author: Fredrik Dahlgren Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 Lund, Sweden Department of Computer Engineering, Lund University, P.O. Box 118, S-221 00 Lund, SwedenView Profile Authors Info & Claims ACM SIGSIM Simulation DigestVolume 21Issue 3April 1991 pp 40–49https://doi.org/10.1145/106073.306841Online:01 April 1991Publication History 2citation179DownloadsMetricsTotal Citations2Total Downloads179Last 12 Months5Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A simulation model that supports very accurate modeling of multiprocessors with a hierarchical, packet-switched interconnection network and private caches is explored. The simulation system contains workload simulators and a memory system simulator. The workload simulators are program-driven, i.e. they actually execute programs. The time unit of the simulator is the time between two consecutive memory references from the processors. The performance of the simulation model, although acceptable, could be improved using a trace-driven approach. The author shows that results obtained from trace-driven simulation methods in the course of multiprocessor performance evaluation are generally not valid. Furthermore, he shows that in the evaluation of certain processor architectural features, such as non-blocking architectures, the program-driven approach is necessary.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Mobile ad hoc networks (MANETs) consist of a collection of wireless mobile nodes which dynamically exchange data among themselves without the reliance on a fixed base station or a wired backbone network. All nodes are mobile and can be connected dynamically in an arbitrary manner. There is no static infrastructure such as base station. All nodes of these networks behave as routers and take part in discovery and maintenance of routes to other nodes in the network. There are various protocols for handling the routing problem in the ad hoc wireless network environment. In this paper, focus is given on studying the performance evaluation of various routing protocols using Qualnet simulator 5.0.2. The performance of the proactive, reactive and hybrid protocols are analyzed with different node densities for stationary nodes. The metrics used for the performance evaluation include throughput, packet delivery ratio and average end to end delay. Key words: Proactive, reactive, hybrid, performance evaluation, Qualnet, end-to-end delay, throughput, packets delivery ratio.

The performance of cache-based multiprocessors for general-purpose computing and for multitasking is analyzed with simple throughput models. A private cache is associated with each processor, and multiple buses connect the processors to the shared, interleaved memory. Simple models based on dynamic instruction mix statistics are introduced to evaluate upper bounds on the throughput when independent tasks are run on each processor. With these models, one can obtain a first estimate of the MIPS (millions of instructions per second) rate of a multiprocessor. >

Large scientific collaborations often have multiple scientists accessing the same set of files while doing different analyses, which create repeated accesses to the large amounts of shared data located far away. These data accesses have long latency due to distance and occupy the limited bandwidth available over the wide-area network. To reduce the wide-area network traffic and the data access latency, regional data storage caches have been installed as a new networking service. To study the effectiveness of such a cache system in scientific applications, we examine the Southern California Petabyte Scale Cache for a high-energy physics experiment. By examining about 3TB of operational logs, we show that this cache removed 67.6% of file requests from the wide-area network and reduced the traffic volume on wide-area network by 12. 3TB (or 35.4%) an average day. The reduction in the traffic volume (35.4%) is less than the reduction in file counts (67.6%) because the larger files are less likely to be reused. Due to this difference in data access patterns, the cache system has implemented a policy to avoid evicting smaller files when processing larger files. We also build a machine learning model to study the predictability of the cache behavior. Tests show that this model is able to accurately predict the cache accesses, cache misses, and network throughput, making the model useful for future studies on resource provisioning and planning.

The word-invalidate cache coherence protocol

In main-memory resident index structures, secondary cache misses have a considerable effect on the performance of index structures. Recently, several main-memory resident index structures that consider cache have been proposed to reduce the impact of secondary cache misses. However, they still suffer from full secondary cache misses whenever visiting each level of index trees. In this paper, we propose a new index structure that minimizes the total amount of cache miss latency. The proposed index structure prefetches the grandchildren of a current node. The basic structure of the proposed index structure is from CSB+-Tree that uses the concept of the node group to increase fan-out. However the insert algorithm of the proposed index structure reduces the cost of a split significantly. Also, we show the superiority of our algorithm through performance evaluation.

The recent Energy Efficient Ethernet (EEE) standard and the eBond protocol provide two orthogonal approaches that allow significant energy savings on routers. In this paper we present the modeling and performance evaluation of these two protocols and a hybrid protocol. We first present eeeBond, pronounced ``triple-e bond'', which combines the eBond capability to switch between multiple redundant interfaces with EEE's active/idle toggling capability implemented in each interface. Second, we present an analytic model of the protocol performance, and derive closed-form expressions for the optimized parameter settings of both eBond and eeeBond. Third, we present a performance evaluation that characterizes the relative performance gains possible with the optimized protocols, as well as a trace-based evaluation that validates the insights from the analytic model. Our results show that there are significant advantages to combine eBond and EEE. The eBond capability provides good savings when interfaces only offer small energy savings when in short-term sleep states, and the EEE capability is important as short-term sleep savings improve.

In automatic memory management programming language, the garbage collector is an important feature which reclaims memory that is no longer referenced by the program. The tracing collector performs a transitive closure across the object reference graph. And this process may result in too many cache misses, because the traverse exhibits poor locality. Previous studies have already proposed using software prefetching to improve memory performance of garbage collector. In this work, we studied the characteristic of prefetch instructions on x86 platforms in detail, and proposed a method to control the prefetch ratios by address thresholds. The experimental results show that a further improvement and optimization is obtained by tuning the prefetch ratio. We use these results to devise some guidelines for optimizing the memory performance as well as minimizing the collection pause times.