Test methods for FPGA switching characteristics on GPETE test platform

This paper presents a new methodology developed to automate test and characterization of mixed-signal cores. The main goal is to establish a connection between the test of mixed mode circuits and the respective design, offering to the designer the means to characterize the designed cores using the same interfaces employed during the simulation: SPICE netlists and waveform viewers involved in the design environment, without the need to turn designers into test experts. The work describes a configurable interface between the computer and the device under test (DUT) that enables the translation of the designer testbench into the characterization lab setup using three levels of configuration: DUT, dedicated printed circuit board interface and test equipment. The control of the platform is performed by proprietary software acting over two different areas: workstation layer (control of the test sequence and hardware involved) and design flow interface (interface with simulation tools). This methodology can contribute to reduce the costs related with the automatic test equipment and also the time devoted to test.

The next generation automatic test system (NGATS) is the latest addition to the Integrated family of test equipment (IFTE) developed and managed by product manager, test, measurement and diagnostic equipment (PM TMDE). This is Version 6 of what is commonly known as the Base Shop Test Facility series of systems developed by the off platform, automatic test system program. NGATS is a reconfigurable, general-purpose, mobile, deployable, automatic test system designed to provide sustainment support to all Army weapon systems. This flexible testing platform will finally standardize and reduce the quantity of the Army's ATE systems to one modern tester and improve weapon system availability. It will allow for a decrease in logistical support requirements for ATE systems and the supported weapons systems and increase the mobility, deployability, affordability and supportability, of automated test equipment. NGATS assures compliance with Joint NxTest architecture and will support the agile rapid global combat support (ARGCS) advanced concept technology demonstration (ACTD) by using a common framework for DOD automatic test systems (ATS). Incremental deployment of this system will ultimately modernize and replace three existing test platforms, DSESTS, BSTF (V) 3, and BSTF (V) 5. NGATS will not only support the weapons systems currently fielded but will also support additional weapons systems as they are developed and fielded in the future. The NGATS will initially take advantage of the existing Test Program Sets for legacy weapons systems however new systems and those legacy systems that will remain in the Army inventory will have TPSs designed to take full advantage of the modern NGATS technology. Increment 1 replaces DSESTS and supports the weapons systems in the heavy brigade combat team (HBCT). The TPSs for Abrams, Bradley and other systems will be rehosted to NGATS with significant improvements. Increment 2 replaces BSTF (V) 3 and supports the MLRS, Avenger, Paladin, TOW, SINCGARS, Kiowa Warrior, Ground Based Sensor, G/VLLD, and M1A1 (SRUs) systems. Increment 3 replaces BSTF (V) 5 and supports the Kiowa Warrior and Apache. There has been increased interest in utilizing the IFTE NGATS as an Army organic sustainment support platform. Other systems that are candidates for support are KNIGHT, LLDR, STRYKER, FCS, Firefinder, LOSAT, NLOS, HIMARS, Land Warrior, SHORADS, TAD, and CROWS.

This paper proposes a power integrity control technique for dynamically controlling power supply voltage fluctuations for a device under test (DUT), and demonstrates its effectiveness for eliminating the overkills/underkills due to the difference of power supply impedance between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method injects compensation currents into the power supply nodes on the ATE system in a feed-forward manner such that the ATE power supply waveform matches with the one on the customer's operating environment of the DUT. A method for calculating the compensation current is also described. Experimental results show that the proposed method can emulate the power supply voltage waveform under a customer's operating condition and eliminate 95 % of overkills/underkills in the maximum operating frequency testing with 105 real silicon devices. Limitations and applications of the proposed method are also discussed.

This paper describes a multi-gigahertz test module to enhance the performance capabilities of automated test equipment (ATE), such as high-speed signal generation, loopback testing, jitter injection, etc. The test module includes a core logic block consisting of a high-performance FPGA. It is designed to be compatible with existing ATE infrastructure; connecting to the device under test (DUT) via a device interface board (DIB). The core logic block controls the test module's functionality, thereby allowing it to operate independently of the ATE. Exploiting recent advances in FPGA SerDes, the test module is able to generate very high (multi-GHz) data rates at a relatively low cost. In this paper we demonstrate multiplexing logic to generate higher data rates (up to 10Gbps) and a low-jitter buffered loopback path to carry high speed signals from the DUT back to the DUT. The test module can generate 10Gbps signals with ~32ps (p-p) jitter, while the loopback path adds ~20ps (p-p) jitter to the input signal.

To get better anti-jamming ability, the emission signal and array calibration signal of the Frequency Synthesizer need to work in pulse mode. To achieve miniaturization and function integration, the ability to generate FSK signals and PSK signals is also needed. To realize the real-time control, the network interface is selected as the medium. The features above make it impossible to measure the Frequency Synthesizer relying on test equipments at this stage. An automatic test system (ATS) based on PXI & LXI hybrid architecture is designed as a solution. Trigger distribution module is created to establish the synchronous measurement mechanism between the ATS and the Frequency Synthesizer. Network communication module is produced, which could send control commands to the Frequency Synthesizer and store fault monitoring information. The test methods of transmission power, spur rejection and harmonic rejection are realized based on zero-span mode and time-gate mode respectively. The FSK signal is demodulated by the sliding FFT method, and the PSK signal is demodulated by the Costas loop method. The accuracy and effectiveness of the test methods are verified through practical application. Besides, on the premise that temperature changes and response nonuniformity are included in the test results, the maximum deviation of transmission power is ±0.175dB within 100 discrete measurements, which could demonstrate the stability of the ATS.

The purpose of this paper is to present a conceptual approach and to make practical recommendations on how to improve the current Automatic Test Equipment (ATE) testing and maintenance capabilities by utilizing the existing cloud computing model to build a globally linked ATE maintenance system. The basic tenet of the ATE community is to support a multi-tiered maintenance concept which, in general, is a three tiered system that is composed of organizational maintenance (O-level), intermediate maintenance (I-level), and depot maintenance (D-level) organizations. The goal of the ATE is to (1) quickly and accurately detect and isolate each fault, (2) provide software tools for analyzing historical data, and (3) gather, manage, and distribute accurate and reliable maintenance information for the failed Unit Under Test (UUT). The ATE system should provide services that will (1) maintain a repository of information that will improve fault detection and isolation, allow for off-platform assessments, document failures, and help quantify corrective actions, (2) reduce false UUT pulls, and (3) reduce repair time by prompting repair procedures. Furthermore, the ATE system should provide additional services that will help optimize the time to diagnose problems by using collected failure information and by recommending entry points into the Test Program Set (TPS) software. It should also present information to the ATE maintainer to aid in informed repair decisions which could be in the form of pilot debrief results, platform Built In Test (BIT) results, O-level test outcomes and corrective actions, and maintenance and usage history of the platform and UUT. So, based on this definition of ATE maintenance the use of cloud computing can be used to provide services to improve the overall ATE testing throughput which will result in bottom line improvements to ATE life cycle costs. By using cloud computing, which is defined to be “a model for enabling ubiquitous, convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be rapidly provisioned and released with minimal management effort or service provider interaction”, users can develop cloud computing models that will provide access to application software and databases that can be used to build a globally linked ATE maintenance system. This paper will discuss the essential characteristics of the cloud computing models and define the various flavors of cloud offerings available to designers today. This paper will also analyze the cloud computing model to arrive at a conceptual approach that can be used to enhance the current ATE Testing and Maintenance capabilities. Practical recommendations will be discussed on how to transform the current ATE Testing and Maintenance capabilities into the specific cloud computing model offerings in order to help configure a globally linked ATE maintenance system.

Virtual test (VT), allowing the verification of test programs and associated test hardware in a simulation environment before silicon and without a real automatic test equipment (ATE), has proven to be an effective technique to cut time-to-market and costs for mixed-signal system on chip (SoC), even in an industrial environment. Mixed-signal VT requires behavioral models both for the device under test (DUT) and the device interface board (DIB), interfacing the DUT with the ATE. Test engineers are used to design the DIB circuitry in detail. The resulting schematic is used for the layout and manufacturing of the DIB. In order to develop a behavioral model of the DIB, the test engineer has (1) to abstract this low-level schematic, by identifying the relevant functions and signal flows, and (2) to write the model manually. This bottom-up procedure is very time consuming and may lead to inconsistencies and errors. This paper introduces a new top-down flow for DIB development, allowing the automatic generation of the DIB behavioral model using VHDL as the modeling language. Test engineers enter the design of the DIB by a schematic entry tool at a very abstract level (i.e. as a block diagram). Using specific libraries, test engineers can then generate the real circuit schematic or VHDL model by dedicated netlisters.

Comprehensive waveform generation is an important functional component of automated test equipment (ATE). Waveform generators synthesize signal stimuli to be applied to a device under test (DUT). As military and commercial electronics become increasingly complex, more sophisticated signal stimuli are required. ATE requires signal stimuli varying from advanced communication signals to the playback of captured real-world analog signals. Waveform generators can synthesize signals that can be broadly categorized into four types: standard functions, advanced functions, arbitrary waveforms, and waveform sequences. Standard functions include the simple sine, square, triangle, pulse, and ramp waveforms. Advanced functions include complex signals such as multi-tone, AM, FM, sinc pulse, haversine, half-cycle sine, Gaussian pulse, Lorentz pulse, noise and others. Arbitrary waveforms involve the point-by-point user-defined waveform synthesis. Waveform sequences provide a mechanism to piece together standard or arbitrary waveforms in stages to create a user-defined compound waveform. Example applications for each of these four waveform categories are described in this paper. Modern waveform generators are extremely powerful, but can also add significant complexity for the user. The arbitrary waveform generator, an instrument found in most ATE systems, is a very powerful signal synthesis tool. Unfortunately, many users take advantage of only a small fraction of the powerful features available to them in an arbitrary waveform generator. Also, selecting the right arbitrary waveform generator can be daunting when comparing specifications such as DAC resolution, clock rates and topology, memory depth, sequencing, sweeping, triggering and synchronization. This paper describes the technical differences between various signal generation techniques, presents the signal fidelity impact of clock topology, discusses dynamic range limitations due to noise, accuracy and resolution, and provides typical applications to illustrate signal generation usage. Ultimately, this information should help the user avoid common pitfalls in applying waveform generators within ATE.

The complexity of electronic-device testing varies widely, ranging from the simplest type manual testing to the most complex Automatic Test Equipment (ATE). Presently power controllers for electrostatic precipitator at industry are tested using simulators at the E-shop and controller development lab. The simulated inputs and outputs are generated manually through mechanical keys and push button switches. The verification process and documentation are also done manually and hence time consuming. To overcome these disadvantages, an intelligent, multipurpose simulator cum test equipment was proposed. ATE was developed using LPC2378 ARM processor with required input and output channels. The ATE has multiple communication interfaces like RS485, RS 232, CAN and Ethernet. It is also provided with Liquid Crystal Display (LCD), keypad and Local Area Network (LAN) communication. ATE completes the testing of controller without any manual intervention. Upon completion of testing, ATE sends out test reports to any computer connected to its LAN Port. The test report is generated in the form of Hyper Text Markup Language(HTML) pages with time stamping and controller particulars.

Manufacturing testing uses various methodologies to validate the product specifications. Some of the production specifications require extensive characterization using two or more parameters. The most common parameters are testing voltage, frequency and temperature across different margins to understand the operating region of the DUT (Device under Test) and apply the correct guard band to the tests to minimize customer defects. Schmoo Plots is one of the validation methodology analysis is a common way of characterizing a device over a range of parameters Voltage, frequency, and temperature. Schmoo plots are collected over multiple corners. Traditionally, the data extracted from testing is manually reviewed to identify marginality and corner cases. Visual review of the schmoo logs is time consuming. Task becomes tedious with increase in the sample space (no of units to get confidence In the testing). In addition manual reviews tend to miss corner cases and the defect shows up very late during product testing. Our approach is to use machine language algorithms to design a Schmoo analyzer model to detect Schmoo plots automatically. The Schmoo Analyzer makes efficient use of Schmoo data logs, by identifying consistently passing automatic test equipment (ATE) test patterns, Schmoo wall, schmoo floor. This helps in faster turn-around time for, Module test development, reject validation and eliminates the need for manual analysis. Based on our testing we are able to obtain an efficiency of 96% with a trained model with product data and efforts continue to improve the predictability that will result testing efficiency.

Load board verification is normally performed by IC manufacturers on an automatic test equipment (ATE) as per of the standard test procedure prior to final test. Since test load boards are used as an interface between the automatic test equipment (ATE) and integrated circuit (IC), it is thus important to ensure that a particular load board is functioning otherwise the test integrity of all IC tested using the board will be questionable. As load boards become increasingly complex and difficult to verify accurately, IC manufacturers may need to use in-circuit testing as an addition to load board verification. Traditional in-circuit test platforms are expensive to implement due to cost in the bed-of-nails fixture. With the introduction of flying-probe in-circuit test platforms, this option is now a cost-viable solution. This paper discusses the issues that surround the combined test strategy of flying-probe in-circuit test and load board verification on an ATE. It goes on to propose a structure test strategy to combine both test platforms. Finally, the results and discussion are presented.

The aim of this master thesis is to develop a high-bandwidth current sensor for a nominal design current of 100 A and a nominal design bandwidth of 100 MHz. After an analysis which properties are important to develop a current sensor, a requirement list was stated. Several current sensing methods were described and their qualification for the stated requirements were evaluated. With the resulting sensing concept, consisting out of Rogowski coils and magneto resistors, a system design was elaborated. One requirement was to develop a current sensor which needs less effort in series production than a regular Rogowski coil. Therefore, a planar Rogowski coil was proposed for this sensor development. Furthermore, a magnetic field simulation was designed. Based on the results, a optimal placement simulation for both sensors was carried out. In the final design phase, the galvanic insulation requirements of 4.8 kV based on the corresponding standards were investigated and implemented. The test equipment used in this thesis was designed and build in-house at IPE (KIT-ADL). Commercial solutions did not offer the suggested requirements for generating a double pulse with the necessary rise time to characterize the current sensor’s bandwidth. The test equipment was able to apply pulses with a maximum current of 200 A and a rise time of 1 ns to the device under test. The prototype is able to sense a current up to ±100 A with a bandwidth of 20 MHz.

A solution for testing fast-switching bidirectional signal lines using an array of technology-specific transceivers has been described previously (1998). This method uses an active component located between the device-under-test (DUT) and the automated test equipment (ATE) to reduce electrical interconnect delays to less than 150 ps. In this paper, the transceiver array concept is extended to include higher-level test processes such as real-time algorithmic pattern generation (APG), multi-gigahertz signal multiplexing, and others. The active test component is therefore called a "Test Support Processor" (TSP). It greatly reduces the functionality and performance capability required of the ATE, while maintaining signal integrity, and improving overall test quality. In its minimum configuration, the TSP provides an array of technology-specific transceivers very close to the DUT. This reduces transmission line effects, allowing for at-speed test of fast I/O switching characteristics. This technique may lead to lower-cost. The TSP is specifically intended to complement and support existing DFT and BIST structures within the DUT. The use of the TSP provides an additional degree of freedom for partitioning the test problem, and may result in a significant paradigm shift for future ATE architectures. This paper describes variations of the TSP concept, its potential applications, and economic impact. Three variations are illustrated through prototype demonstrations, including: (A) a 2.67 Gbps test pattern source, (B) a transceiver array for testing a high speed 4 Mbit SRAM, and (C) a reconfigurable real-time APG for memory testing, implemented using a field-programmable gate array (FPGA).

This paper describes repeatability problem and uncertainty which occurs in radiated emission test according to EMC standard EN 55022 while Equipment Under Test (EUT) and Auxiliary Equipment (AE) are communicating by using High Definition Multimedia Interface (HDMI). Nowadays nearly all multimedia equipment has at least one HDMI port and this port is very sensitive in terms of EMC tests, especially in radiated emission test. Emission comes out from mainly the clock line during the tests. Therefore main frequency and its harmonics have a big effect on the test results. Many EMC laboratories are coming across a catastrophic problem when they want to arrange a robust setup according to standards, since there are several ingredients which have big influence on the test results. To compare the effect of HDMI cable and AE on the emission level, the same equipment (television as an EUT) was tested with different HDMI cables and auxiliary equipment. Also effect of HDMI cable position to emission level is tested by using same EUT and AE. The same problem is occurring easily when tests are performed according to new EMC standard EN 55032 which supersedes EN 55022 and EN 55013. To eliminate the effect of cable positions and to ensure the setup remains stable, disturbance values emitted from the cable at HDMI clock frequency and its harmonics were measured by using disturbance power test setup according to CISPR 16-2-2. Whether EUT has low emission or not, the EUT can pass or fail radiated emission test. When you repeat the tests even in the same laboratory, results are in a wide range of margins with an unacceptable uncertainty budgets.

Testing devices at clock rates exceeding 50 MHz with waveform resolution below 100 ps necessitates the use of sampling methods. The current state of the art includes two radically different sampling technologies: electronic sampling (ES) utilizing a diode bridge structure and a novel electrooptic sampling (EOS) technology which uses short light pulses as the time-resolving element. The bandwidth, loading, and time/voltage accuracy of these two technologies are compared for fitness of use in a gigahertz ATE (automatic test equipment) environment. It is noted that the analysis of these two techniques quantifies the electrooptic technology's time accuracy advantages due to its low loading and short DUT (device under test)/sensor distances. >