Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques

We present a testable built-in self test(BIST) design for phase-lock loop(PLL). The design can measure the clock jitter for PLL with high precision and high accuracy due to better utilization of the test integration and test subtraction techniques. Although the BIST circuit is implemented by all digital standard cells to achieve better reliability, it can even be applied to measure the analog clock jitter. Besides, for some DfT (design for test) techniques inserted to make BIST itself testable, we discuss the trade-off among area, timing, number of test patterns and fault coverage in this paper.

In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.

Built-in self test (BIST) techniques are widely used in today's complex integrated circuits, since they employ on-chip test pattern generation and response verification. Arithmetic BIST techniques utilize modules that commonly exist in datapath modules (accumulators, counters etc.). In order to perform the test generation and response verification operations. In order to detect sequential faults that occur into current CMOS circuits, two-pattern tests are required. Furthermore, delay testing, commonly used to assure correct temporal circuit operation at clock speed, requires two-pattern tests. In this paper a novel algorithm for the generation of two-pattern tests is presented. The presented algorithm utilizes modules included in datapath circuitry to generate two-pattern tests; its implementation in hardware compares favorably with techniques that have been presented in the open literature

Current trends in VLSI designs necessitate low power during both normal system operation and testing activity. Traditional Built-in Self Test (BIST) generators rise unnaturally the power consumption during testing, boosting the need to add low-power solutions to the arsenal of BIST pattern generators. In this paper, the utilization of gray code generators is proposed as a low-power BIST solution. More precisely, we show how the time required to apply a given test pattern can be decreased, by switching between different gray sequences during the application of the test set. Experimental results indicate that the time required to embed the test set within a low-power sequence is reduced to almost 50%, compared to a previously proposed solution.

Testing high-speed analogue and mixed-signal designs, in particular, is becoming a more difficult task, and observing critical nodes in a system is becoming increasingly challenging. As the technology keeps scaling, especially past the 90 nm technology, metal layers and packing densities are increasing as a function of signal bandwidth and rise times extending beyond the gigahertz range. Automatic test equipment (ATE) interface has become a major bottleneck to deliver signals with high fidelity, due to the significant distances the signals have to travel at such operational speeds. Test solutions can be placed on the chip and are then known as a structural test or built-in self test (BIST), on the board level or as part of the requirements of the ATE.

A new technique called input reduction is proposed for built-in self test (BIST) test pattern generator (TPG) design and test set compaction. This technique analyzes the circuit function and identifies sets of compatible and inversely compatible inputs; inputs in each set can be combined into a test signal in the test mode without sacrificing fault coverage, even if they belong to the same circuit cone. The test signals are used to design BIST TPGs that guarantee the detection of all detectable stuck-at faults in practical test lengths. A deterministic test set generated for the reduced circuit obtained by combining inputs into test signals is usually more compact than that generated for the original circuit. Experimental results show that BIST TPGs based on input reduction achieve complete stuck-at fault coverage in practical test lengths (/spl les/2/sup 30/) for many benchmark circuits. These are achieved with low area overhead and performance penalty to the circuit under test. Results also show that the memory storage and test application time for external testing using deterministic test sets can be reduced by as much as 85%.

The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

Numerous Built-In Self Testing (BIST) designs now exist for the testing of Programmable Logic Arrays (PLA), but their practical usefulness has not been studied. In this paper, we implement and compare several BIST designs using a common methodology of implementation. We also perform an yield analysis to characterize the yield degradation due to the BIST design methodology. Our preliminary findings of this work is that BIST approach results in considerable degradation of yield, and therefore may not be suitable as a test vehicle for PLAs.

In this research, a BIST (built in self test) architecture for testing crosstalk effects in highly dense Through Silicon Via (TSV) placed in structured array form, in 3DICs (Three Dimensional integrated circuits), designed and simulated using the Xilinx ISE tool and the VHDL language. A novel methodology is proposed, and simulated, to observe the test responses of the victim TSVs in the chosen group simultaneously. Boundary-scan cell structures are modified, created for the purpose of operating in different modes such as shift, update and capture in either conventional serial shift mode as well as in proposed parallel broadcasting mode. Output Response Analyzers (ORA), or signature analyzers that have been simulation-verified. In this study, we suggested a novel encoder-based signature generator to locate faulty TSVs in the parallel-observed TSVs. This paper discusses the whole BIST architecture, the BIST controller built on an algorithmic state machine, the design of TPG (Test Pattern Generator), and the faulty TSV signature generator. Comparing the BIST architecture, to serial shift based interconnect tests done by IEEE 1149.1 (JTAG) such as EXTEST and IEEE 1838 standards, the test’s time complexity of BIST is relatively very low. The entire TSV array test is completed in just 32 clock cycles. The design is adaptable and can be used to broadcast test patterns to a group or to transmit test patterns serially using IEEE 1838 or 1149.1.

In this paper, we present a new RF built-in self test (BIST) circuit for 865–870 MHz low noise amplifiers (LNAs); The BIST and LNA circuit is designed using 0.35µm CMOS technology. The simple circuit of test that contains a RF peak detectors and two comparators brings high fault coverage. The faults simulating possible catastrophic and parametric faults are introduced. A total of twenty eight short and open faults and ten parameters variation have been introduced into the LNA, giving fault coverage of 89% for catastrophic faults and 90% for process variation.

DRAM testing is of major importance in systems reliability. Effective fault models, like the Neighborhood Leakage and Transition Fault (NLTF) model, can be exploited for DRAM testing. An efficient NLTF-based Built-In Self Test (BIST) circuit, for the acceleration and simplification of DRAM testing procedures, is presented in this work.

Linear dependency check in built-in test

We present a novel approach for built-in self test (BIST) for VLSI. Many conventional BIST schemes use signatures generated by a linear feedback shift register (LFSR) or a multiple input signature register (MISR) for determining whether the device under test is faulty or fault free. In the approach presented, fault detection is made based on the number of different states the LFSR visits. This number is called the cycle length. It is also shown that such an approach results in the probability of aliasing of 2/sup -(2m-1+m/), where m denotes the number of registers in the LFSR, compared to 2/sup -m/ achieved by conventional signature analyzers. We also present the complexity of the additional hardware required to implement the scheme.

HIERARCHICAL SELF TEST FOR SOCS INCLUDING LOGIC AND INTERCONNECTS

This paper represents an innovative solution to reduce phase noise present on the GMSK modulated spectrum in an all-digital RF transmitter employing a discrete-time oscillator. The root cause of this issue is the improper timing of oscillator tuning word update with respect to the digitally-controlled oscillator (DCO) capacitor state. Using the built-in self test (BIST) circuit in the all-digital PLL (ADPLL), the DCO tuning word update timing is calibrated such that the impact on the phase noise is compensated and desired modulated spectrum margin from the specification is achieved