The CCSDS Decoder/Encoder Boards

Chapter 1 - Operation of a microcomputer

Cache memory has grown to be an essential component of CPU architecture due to the growing gap between processing power and main memory access latency. The cache design that processors use has numerous levels, with the smallest, fastest private caches (Level 1) supported to the largest, slowest caches (Level 2). Snoop Control Units (SCUs) have been added to multi-core processors to ensure the coherency of private cache data. The literature that is currently available discusses application-specific cache alignment methods. When inter-core communication begins to function at the OS level, Symmetric Multi-Processing (SMP)/Asymmetric Multi-Processing (AMP) Real Time Operating Systems (RTOS) will add a significant amount of overhead to system activities. This study is the first to propose an unique signalling technique between the cores based on cache aware information lookups. It is implemented as "SCHEDULE-ASSIST" and "ENTITY-ASSIST" in the Little Kernel scheduler, an SMP RTOS scheduler. We demonstrate an up to 13% improvement in RTOS processing Key Performance Indices (KPI) for RTOS’ Application Programming Interfaces (APIs) compared to schemes that are unaware of the cache design through analytical modelling and implementation using a Xilinx Evaluation Kit.

The complexity of consumer electronics devices have them employ more powerful processors as their processing load becomes higher; thus, their higher power consumption becomes a critical problem. In order to balance processing power and electrical power consumption, heterogeneous multi-core processors are becoming popular. This paper proposes an extensible RTOS (real-time operating system) architecture for such heterogeneous multi-core processors, which consist of processors with different processing power and functionalities. The architecture splits the RTOS kernel into the two components, the proxy kernel (PK) and user-level kernel (UK), and decouples dynamic resource management functions from the PK. Such architecture enables the PK to run on a less powerful core while RTOS can utilize dynamic resource management functions provided by the UK. The experiment results running micro benchmark programs show the feasibility of the proposed architecture.

Existing real-time multicore schedulers use either global or partitioned scheduling technique to schedule real-time tasks. Partitioned scheduling is a static approach in which, a task is mapped to a per-processor ready queue prior to scheduling it and it cannot migrate. Partitioned scheduling makes ineffective use of the available processing power and incurs high overhead when real-time tasks are dynamic in nature. Global scheduling is a dynamic scheduling approach, where the processors share a single ready-queue to execute the highest priority tasks. Global scheduling allows task migration which results in high scheduling overhead. In this paper, we present a dynamic partitioning based scheduling of real-time tasks, called DP scheduling. In DP scheduling, jobs of tasks are assigned to cores when they are released and remain in the same core till they finish execution. The partitioning in DP scheduling is done based on the slack time and priority of jobs. If a job cannot be allocated to any core, then it is split, and executed on more than one core. DP scheduling technique attempts to retain good features of both global and partitioned scheduling without compromising on resource utilization, and at the same time, also tries to minimize the scheduling overhead. We have tested DP scheduling technique with EDF scheduling policy at each core, and we term this scheduling algorithm as DP-EDF. The performance of DP-EDF scheduling algorithm has been evaluated using simulation study and its implementation in LITMUS-RT on a 64-bit intel processor with eight logical cores. Both simulation and experimental results show that DP-EDF scheduling algorithm has better performance in terms of resource utilization, and comparable or better performance in terms of scheduling overhead in comparison to contemporary scheduling algorithms.

Autonomous control systems onboard planetary rovers and spacecraft benefit from having cognitive capabilities like learning so that they can adapt to unexpected situations in-situ. Q-learning is a form of reinforcement learning and it has been efficient in solving certain class of learning problems. However, embedded systems onboard planetary rovers and spacecraft rarely implement learning algorithms due to the constraints faced in the field, like processing power, chip size, convergence rate and costs due to the need for radiation hardening. These challenges present a compelling need for a portable, low-power, area efficient hardware accelerator to make learning algorithms practical onboard space hardware. This paper presents a FPGA implementation of Q-learning with Artificial Neural Networks (ANN). This method matches the massive parallelism inherent in neural network software with the fine-grain parallelism of an FPGA hardware thereby dramatically reducing processing time. Mars Science Laboratory currently uses Xilinx-Space-grade Virtex FPGA devices for image processing, pyrotechnic operation control and obstacle avoidance. We simulate and program our architecture on a Xilinx Virtex 7 FPGA. The architectural implementation for a single neuron Q-learning and a more complex Multilayer Perception (MLP) Q-learning accelerator has been demonstrated. The results show up to a 43-fold speed up by Virtex 7 FPGAs compared to a conventional Intel i5 2.3 GHz CPU. Finally, we simulate the proposed architecture using the Symphony simulator and compiler from Xilinx, and evaluate the performance and power consumption.

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

TriOS operating system

A real-time operating system, the Ada Avionics Real-Time Software (AARTS) Operating System (AOS), is discussed, which under development for the US Air Force. The AOS is intended to mitigate problems with Ada executing in real time on 16-bit data processors in a distributed architecture configuration. The AOS consists of a three part executive: system executive, kernel executive, and distributive executive. Each is described along with AOS operation and system functions. >

Increasingly, real-time systems are being used in applications that contain tasks that have deadlines and require predictable performance. Many complex real-time applications require modern operating systems capable of scheduling multiple classes of tasks in an integrated way. These applications require scheduling that result in high utilization of available processing power to accommodate as many tasks as possible while satisfying the required deadlines of each task. In this paper, we propose a combined heuristic approach to schedule a set of independent soft and hard real-time tasks in multiprocessor computing systems. Each of these tasks is characterized by its arrival time, deadline and required processing power. The proposed approach distributes the total available processing power of any processor, if it is needed and possible, among more than one task, while ensuring that hard real-time tasks are given higher priority and enough processing power to meet deadlines. This strategy can be used as a tool to efficiently guide scheduling processes. In addition, it can help to optimize processor utilization and maintain higher success ratios by maximizing the schedulability of soft tasks without jeopardizing the schedulability of hard tasks.

System design kit for the 8051

Real-time Linux operating system for plasma control on FTU—implementation advantages and first experimental results

This paper presents an FPGA hardware implementation of a bar code decoder using the EAN-13 standard. The design was implemented on an FPGA situated on an ATMEL FPLSIC (field programmable system level integrated circuit, AT94K40-25DQC). The design has comparable performance and is in many ways more robust than commercially available devices. However, to the authors' knowledge, these all use a microprocessor while our design is purely dedicated hardware.

In recent years, the embedded system has become a common goal sought by the academic world such as computer science, electronics, electrical engineering... etc or product developers. As we enter into the post-PC era, advances in electronics, information technology, and mobile computing provide the basis for the development of embedded systems and related products. This paper documents all relevant knowledge and procedures related to the modeling of a system structure, from the selection of main hardware control components ARM and FPGA, the construction of a workable hardware system, programming of drivers, implementation of a real-time operating system and the running of applications, to the final hardware and software testing of the entire system. The structuring of a system is not the most complicated, but the most fundamental. Our aim is to provide references for researchers studying in this particular field.

With the wide-spread using of LinuxOS, the Real-time requirement in certain applications is heighly demanded. So the Xenomai comes up, it has a higher priority than Linux kernel, so it can deal with the tasks which need real-time requirement.In order to set up the real-time Linux based on the ARM platform, the mini2440 development board contained s3c2440 as its MCU is used to set up the real-time operation system. Design and test the performs of the system. The results show that the embeded real-time Linux system based on the Xenomai has the good quality of real-time and can be used in the soft real-time system or the hard real-time system.

Many modern embedded applications need the execution support of a real-time operating system. Such applications have usually critical or hard timing requirements, but giving the high presence of multimedia devices, real-time operating systems can also be used to manage the tasks that execute within multimedia devices. This paper focuses on identifying the requirements of a real-time operating system capable of fulfilling the needs of the multimedia applications typically executed on multiprocessor, mobile-oriented systems such as the Movidius platform.