The Formal Design Models of a Universal Array (UA) and its Implementation

Graphs are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. Problems in sciences and engineering can be formulated and solved by the graph model. This paper develops a comprehensive design pattern of formal digraphs using the Doubly-Linked List (DLL) architecture. The most complicated form of graphs known as the weighted digraph is selected as a general graph model, based on it simple graphs such as nondirected and/or nonweighted ones can be easily derived and tailored. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of digraphs to be rigorously designed and implemented in a top-down approach. The architectural models of digraphs are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of digraphs is implemented using nodes of DLL dynamically created in the memory. The behavioral models of digraphs are specified and refined by a set of 18 Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node manipulation operations. This work has been applied in a number of real-time and nonreal-time system designs and specifications such as a Real-Time Operating System (RTOS+), graph-based and tree-based applications, and the ADT library for an RTPA-based automatic code generation tool.

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers; the conceptual and architectural models of RTOS+ is described in this paper, while the static and dynamic behavioral models of RTOS+ will be elaborated in a forthcoming paper.

Trees are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. A binary tree (B-Tree) is a typical balanced tree where the fan-out of each node is at most two known as the left and right children. This paper develops a comprehensive design pattern of formal trees using the B-Tree architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of B-Trees to be rigorously designed and implemented in a top-down approach. The architectural models of B-Trees are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of B-Trees is implemented using the left and right child nodes dynamically created in memory. The behavioral models of B-Trees are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a general system organization model, and the ADT library for an RTPA-based automatic code generator.

A Lift Dispatching System (LDS) is a typical real-time system that is highly complicated in design and implementation. This article presents the formal design, specification, and modeling of the LDS system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the LDS system is introduced as the initial requirements for the system. The architectural model of the LDS system is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of the LDS system are specified and refined by a set of Unified Process Models (UPMs) for the lift dispatching and serving processes. The dynamic behaviors of the LDS system are specified and refined by process priority allocation and process deployment models. Based on the formal design models of the LDS system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transferred into programs by programmers. The formal models of LDS may not only serve as a formal design paradigm of real-time software systems, but also a test bench of the expressive power and modeling capability of exiting formal methods in software engineering.

Files are a typical abstract data type for data objects and software modeling, which provides a standard encapsulation and access interface for manipulating large-volume information and persistent data. File management systems are an indispensable component of operating systems and real-time systems for file manipulations. This paper develops a comprehensive design pattern of files and a File Management System (FMS). A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of files and FMS to be rigorously designed and implemented in a top-down approach. The conceptual model, architectural model, and the static/dynamic behavioral models of files and FMS are systematically presented. This work has been applied in the design and modeling of a real-time operating system (RTOS+).

Real-time process algebra (RTPA) is a denotational mathematical structure for denoting and manipulating system behavioral processes. RTPA is designed as a coherent algebraic system for intelligent and software system modeling, specification, refinement, and implementation. RTPA encompasses 17 metaprocesses and 17 relational process operations. RTPA can be used to describe both logical and physical models of software and intelligent systems. Logic views of system architectures and their physical platforms can be described using the same set of notations. When a system architecture is formally modeled, the static and dynamic behaviors performed on the architectural model can be specified by a three-level refinement scheme at the system, class, and object levels in a top-down approach. RTPA has been successfully applied in real-world system modeling and code generation for software systems, human cognitive processes, and intelligent systems.

Real-time process algebra (RTPA) is a form of denotational mathematics for dealing with fundamental system behaviors such as timing, interrupt, concurrency, and event/time/interrupt-driven system dispatching. Because some key RTPA processes cannot be described adequately in conventional denotational semantic paradigms, a new framework for modeling time and processes is sought in order to represent RTPA in denotational semantics. Within this framework, time is modeled by the elapse of process execution. The process environment encompasses states of all variables represented as mathematical maps, which project variables to their corresponding values. Duration is introduced as a pair of time intervals and the environment to represent the changes of the process environment during a time interval. Temporal ordered durations and operations on them are used to denote process executions. On the basis of these means, a comprehensive set of denotational semantics for RTPA are systematically developed and formally expressed.

Software architecture is receiving increasingly attention as a critical design level for software systems. However the current practice of architectural description is largely informal and ad hoc, with the consequence that architectural documents serve as a poor communication mechanism, are difficult to analyze, and may have very little relationship to the implemented system. In an attempt to address these problems several researchers have experimented with formalisms for architectural specification and modelling. One such formalism is the WRIGHT specification language. In this paper, we show how WRIGHT can be used to provide insight into an architectural design by modelling a prototype implementation of part of the AEGIS Weapons System (AWS).

Formal architecture modeling of sequential non-recursive C programs

Model-driven engineering methodologies are often used for the design and integration of the software and hardware components in automated production systems. Architecture models in general purpose or domain specific modeling languages allow the modular and systematic construction of formal analysis models for the evaluation of dependability and performability. The on-line reconfiguration and fault handling actions in the system introduce changes in the architecture and parameters, and thus result in a multi-phased operation. We propose a mission automaton formalism to describe reconfigurations, fault handling and parameter changes over architecture models. By maintaining the architecture model, which is modified by the reconfigurations, along with the corresponding analysis models, a stochastic phased-mission system (PMS) is obtained and solved for dependability.

В настоящее время широкое распространение получила микросервисная архитектура, появляется множество приложений (микросервисов), которые так или иначе между собой взаимодействуют. Микросервисы, как правило, объединяются в целые платформы. Встает острый вопрос взаимодействия их друг с другом, хранения и обмена справочными данными. Эталонного решения данной проблемы не существует, на данный момент, но в данной работе описан симбиоз различных подходов, а также приведена конкретная реализация – унифицированная модель справочников в микросервисной платформе, которая позволяет обмениваться справочными данными десяткам микросервисов (на момент написания статьи количество сервисов в платформе составляет 57 штук). Была спроектирована метамодель, с помощью которой описываются сущности справочников: справочники, категории, связи между справочниками и между сущностями справочников. Архитектура такой модели микросервиса справочников позволяет абстрагироваться от конкретных реализаций СУБД, таким образом не происходит «сильной связности» с SQL или NoSQL базой данных. Данный микросервис имеет искусственно введеные ограничения запись данных от сторонних микросервисов. Миграция данных осуществляется вручную посредством Liquibase скриптов, что позволяет поддерживать справочники в одинаковом состоянии на всех стендах разработки, быстро и легко восстанавливать до любого состояния слепки справочников. Дальнейшее развитие микросервиса справочников может иметь следующий вид: разработка UI форм для ручного заполнения справочников и сохранение новых данных в модели или в скрипты Liquibase, что уже на данном этапе является очень актуальной проблемой для группы сопровождения и администраторов микросервисной платформы. Today, the microservice architecture has become widespread and most popular in software engineering; many applications (microservices) are forced to communicate with each other. In the future, microservices are combined into entire application platforms. The acute issue of interaction of microservices with each other, storage and exchange of dictionary data have appeared in the minds of developers. A standard solution to this problem does not exist at the moment, but this article describes the symbiosis of various approaches, and also provides a specific implementation - a unified data model of dictionary in a microservice platform. It allows dozens of microservices to exchange dictionary data (now, the number of services in the platform is 57 pieces). This article describes the metamodel which help to design and create entities of dictionary, there are: category of dictionary, relations between categories and between directories. Such data model architecture of microservice allowed me to abstract from specific DBMS implementations, i.e. I am not hard tied on SQL or NoSQL database. This microservice has artificially introduced restrictions on data recording by other microservices. Data migration is carried out manually by Liquibase scripts, which allows maintaining dictionaries in the same state at all development stands, quickly and easily restore dictionaries to any state. Further evolution of the dictionary microservice could be as follows: the development of a user interface for filling dictionaries by administrator`s hands and saving new data in unify data models or auto generation Liquibase scripts. At this stage this problem is very urgent for the support group and administrators of the microservice platform.

In a model-driven development context, the refinement of the architectural model of a real-time application to a Real Time Operating System (RTOS) specific model is a challenging task. Indeed, the different design choices made to guarantee the application timing properties are not always implementable on the target RTOS. In particular, when the number of distinct priority levels used at the design level exceeds the number allowed by the RTOS for the considered application, this refinement becomes not possible. In this paper, we propose a software pattern called Distinct Priority Merge Pattern (DPMP) that automatically perform the re-factoring of the architectural model when this problem occurs. First, we give an heuristic algorithm describing this pattern and we show that this method is not always effective. Then, to address the limitations of the first method, we propose a MILP formulation of the DPMP pattern that allows to check whether a solution exists and gives the optimal one. The evaluation of the second method, allows to estimate a cost in terms of processor utilization increase during the deployment of an application on a given RTOS family characterized by the number of distinct priority levels that it offers.

A geometric modelling framework for conceptual structural design from early digital architectural models

Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements, and nonuniform communication resources. In order to take hardware and software design decisions, early evaluations of the system nonfunctional properties are needed. These evaluations of system efficiency require electronic system-level information on both algorithms and architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal models of computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a model of architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the linear system-level architecture model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a state-of-the-art multiprocessor system-on-chip (MPSoC) when running an application described using the synchronous dataflow MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%.

Traditional embedded Real-Time Operating Systems (RTOS) or Basic Software (BSW) implementations typically require manual porting to new hardware platforms. However, this approach can be time-consuming and error-prone, especially given the frequent introduction of new or upgraded hardware architectures. In addition, traditional testing methods may not fully capture the complexity and nuances of the system, making it difficult to ensure correctness and dependability. To address these challenges, we propose a comprehensive methodology that integrates formal methods, a WCET tool, and a code generation technique. We use formal methods to create models and verify their correctness against functional and non-functional specifications or properties such as safety, liveness, and timing. We use the WCET tool as a microarchitecture analyzer to analyze the low-level binary code. The intermediate results of the tool are used to verify the correctness of the software implementation against the runtime effects of the hardware, such as data/memory race conditions. Finally, the code is generated from the formal models. Our proposed framework simplifies the maintenance of RTOS or BSW implementations while ensuring their correctness and partially automating portability to new hardware architectures.