The Implementation of Bee Colony Optimization Algorithm to Sheppard–Taylor PFC Converter

Hybrid bee colony optimization for examination timetabling problems

Adjustable-speed drives (ASD) are extensively adopted in industrial power systems due to their ability to enhance overall efficiency by supplying optimal power to motors based on specific speed and torque requirements. While much existing research focuses on conventional diode rectifiers or voltage-source inverters as front-end solutions, this paper introduces a three-phase power factor correction (PFC) approach using a common DC-link voltage for motor drive applications. This innovative method significantly reduces input current harmonics and improves power factor with minimal active switching components and straightforward control strategies. Furthermore, the DC-link bus can be utilized for multiple motor drives as well. Both analytical and simulation studies validate the effectiveness of the proposed system, demonstrating that the input currents achieve a sine wave form with a unity power factor, while total harmonic distortion of the input current (THDi) is minimized to approximately 2% at the rated power level.

A hybrid approach composed by different types of fuzzy systems, such as the Type-1 Fuzzy Logic System (T1FLS), Interval Type-2 Fuzzy Logic System (IT2FLS) and Generalized Type-2 Fuzzy Logic System (GT2FLS) for the dynamic adaptation of the alpha and beta parameters of a Bee Colony Optimization (BCO) algorithm is presented. The objective of the work is to focus on the BCO technique to find the optimal distribution of the membership functions in the design of fuzzy controllers. We use BCO specifically for tuning membership functions of the fuzzy controller for trajectory stability in an autonomous mobile robot. We add two types of perturbations in the model for the Generalized Type-2 Fuzzy Logic System to better analyze its behavior under uncertainty and this shows better results when compared to the original BCO. We implemented various performance indices; ITAE, IAE, ISE, ITSE, RMSE and MSE to measure the performance of the controller. The experimental results show better performances using GT2FLS then by IT2FLS and T1FLS in the dynamic adaptation the parameters for the BCO algorithm.

Bee Colony Optimization metaheuristic for fuzzy membership functions tuning

Present day standards and applications require power electronic ac- dc converters that can operate over a wide range of load variations with approximately unity power factor, controlled dc bus voltage, low input current distortion, and a simple controller. Power factor correction (PFC) techniques can be a practical solution to unidirectional rectifiers since they reduce the number of devices, and improve the efficiency and power system quality as well. This paper presents a new topology of a modular three-phase AC-DC converter. The presented PFC converter can produce a controlled dc output voltage, near-unity power factor, and high efficiency. By operating in the continuous conduction mode (CCM) with an active approach which is one class of high-quality three-phase rectification, the required features are achieved. The performance of the topological structure of the presented converter is discussed and investigated under various modes of operation to identifies their merits and limitations. Extensive simulation is carried out using PSIM software to validate the explained function.

The unique foraging behaviour of bees via waggle dance has been computationally realised as an algorithm named bee colony optimisation (BCO) to solve different types of combinatorial optimisation problems such as travelling salesman problem (TSP). In order to enhance the performance of BCO, local optimisation can be integrated. However, local optimisation incurs high processing overhead especially when all solutions are allowed to undergo the local optimisation. This paper proposes a pruning strategy based on the top-k sequential patterns (TKS) mining algorithm. Specifically, TKS is employed to identify the frequent building blocks along the optimisation process. A total of 19 TSP benchmark problem instances ranging from 318 cities to 1,291 cities were used as the test bed. The proposed pruning strategy shows a significant reduction in terms of the computational time to yield TSP solutions with similar tour length as compared with two state-of-the-art approaches.

This paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by field programmable gate array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-voltage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a pre-regulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400 V nominal output voltage and 220 Vrms nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device

In recent decades, the classification of fake fingerprints and real fingerprint images has become an attractive research topic because of the most advanced threats. A number of research works have been carried out to classify fake and real fingerprints. But, most of the existing techniques did not utilize swarm intelligence techniques in their fingerprint classification system. Swarm intelligence has been widely used in various applications due to its robustness and potential in solving a complex optimization problem. The proposed classification methodology comprises of four steps, namely image preprocessing, feature extraction, feature selection and classification. This work uses efficient min-max normalization and median filtering for preprocessing, and multiple static features are extracted from Gabor filtering. To perform multiple static feature selection, Artificial Bee Colony (ABC) and Modified Artificial Bee Colony (MABC) optimization algorithm is used in this work to choose the best optimal static features on the basis of specific fitness values. This approach uses Fuzzy Feed Forward Neural Network (FFFNN) for classification and classification of feature vector into fake and real fingerprint images by the semi supervised graph based classification approach which enables efficient classification of real and fake fingerprints and its performance is compared with the SVM classifier. Evaluation of the performance has been carried out by taking the fingerprint images that had been collected from the FVC2000 and synthetically generated database by employing the SFinGE. The results showed that the proposed work provided improvised and enhanced results with respective to characteristics like sensitivity, precision, specification as well as classification accuracy.

Research on distributed task planning model for multi-autonomous underwater vehicle (MAUV). A scroll time domain quantum artificial bee colony (STDQABC) optimization algorithm is proposed to solve the multi-AUV optimal task planning scheme. In the uncertain marine environment, the rolling time domain control technique is used to realize a numerical optimization in a narrowed time range. Rolling time domain control is one of the better task planning techniques, which can greatly reduce the computational workload and realize the tradeoff between AUV dynamics, environment and cost. Finally, a simulation experiment was performed to evaluate the distributed task planning performance of the scroll time domain quantum bee colony optimization algorithm. The simulation results demonstrate that the STDQABC algorithm converges faster than the QABC and ABC algorithms in terms of both iterations and running time. The STDQABC algorithm can effectively improve MAUV distributed tasking planning performance, complete the task goal and get the approximate optimal solution.

A bee colony optimization (BCO) algorithm for traveling salesman problem (TSP) is presented in this paper. The BCO model is constructed algorithmically based on the collective intelligence shown in bee foraging behaviour. Experimental results comparing the proposed BCO model with some existing approaches on a set of benchmark problems are presented.

Artificial Bee Colony (ABC) optimization algorithm has captured much attention of researchers from various fields, in recent times. Moreover, various comparative studies clearly reports robust convergence of ABC algorithm than other bio-inspired optimization algorithms. Nevertheless, like other optimization algorithms, ABC suffers from slower convergence and tendency towards local optima trappings. Therefore, various amendments have been proposed to avertthe flaws of ABC algorithm. Nonetheless, the variants are either computationally intensive or could not avert the flaws of the algorithms. Hence, this research work proposes an efficient variant of ABC algorithm. The proposed variant capitalizes on the global-best food-source. The proposed variant has been compared with various existing variants of ABC algorithm on a few benchmark functions. Significance of the proposed variant has also been analyzed statistically. Results show the best convergence of the proposed variant among all the compared optimization algorithms on all benchmark functions.

In this paper three novel control schemes for the single-phase ac/dc converter with two-level or three-level pulse width modulation are proposed to improve the power quality. A diode rectifier with two power switches is adopted as a power factor correction circuit to achieve high power factor and low harmonic distortion. The proposed control schemes are based on look-up tables with a hysteresis current controller instead of the conventional complex control algorithm. The proposed control scheme can (1) draw a sinusoidal line current, (2) achieve a unity power factor and (3) improve voltage unbalance problem on the dc bus capacitors. The software simulations and experimental results are shown to verify the proposed control algorithms. It is shown that the measured harmonic currents and input power factor satisfy the international standard requirements such as International Electrotechnical Commission 1000-3-2.

A comparison of fuzzy self‐tuning (FST), sliding mode control (SMC) and conventional proportional–integral (PI) control methods is performed under unbalanced grid conditions using a bridgeless power factor correction (PFC) converter. The bridgeless PFC converter operates the correction of AC line current to obtain a DC output voltage without full bridge rectifier based on these control methods. These control methods generate the duty cycles to provide higher unity power factor and lower total harmonic distortion of input current, even if AC line voltage is distorted. This study focuses on the performance analysis of FST and SMC methods adaptation to the input current for the bridgeless PFC converter and comparing with the conventional PI controller. Although the SMC method is only used in the current control loop, the FST method is used in both current and voltage control loops for eliminating harmonics of input current and regulating of output voltage. The performance of control methods is evaluated with a TMS320F2812 digital signal processor. The simulation and experimental results are compatible with the limits for harmonic current emissions, IEC 61000‐3‐2 and show that the FST and SMC are better than the conventional PI control method and FST is superior to the SMC.

This paper gives a new insight into the concept of load compensation under distorted voltages. Achieving both unity power factor (UPF) and perfect compensation of current harmonics are not possible where competition will arise between these two important factors. Through evaluating the present control strategies, a generalized, optimal, and flexible control strategy (OFC) for harmonic compensation of utility lines is proposed. The proposed control strategy, which provides a unified and highly flexible compensation framework has the ability of programming for perfect current harmonics compensation, or (UPF) accomplishment, or other newly defined objectives such as maximizing the power-factor subject to some adjustable constraints on the level of current harmonics and unbalancing via an on-line optimization algorithm. The strategy can fulfill the IEEE-519 standards requirements, while guaranteeing the best achievable power factor and optimum required rating for the compensator. Theoretical concepts and practical features of the proposed control strategy have been shown through extensive simulation studies using MATLAB/SIMULINK programs.

To reduce total harmonic distortion (THD) and improve the power factor (PF) of a boost power factor correction (PFC) converter, here, the authors propose a non‐linear control algorithm that includes the feedforward correction (FC) algorithm in the continuous conduction mode (CCM) and the non‐linear frequency variation (FV) algorithm in the mixed conduction mode (MCM). The proposed FC algorithm achieves current out of distortion through zero crossing with a lower current loop bandwidth. The proposed non‐linear FV algorithm achieves high PF and low THD under minimal load conditions. The non‐linear FV algorithm comprises a third harmonic extraction algorithm, a harmonic control loop for reducing THD and a frequency production algorithm. By using this non‐linear FV algorithm, the inductor size is reduced, which leads to lower cost and also achieves better THD and PF. The proposed algorithms are verified experimentally in terms of current tracking, current THD, PF, heating and loss on a 2000‐W boost PFC converter hardware prototype.