THE PHYSICS OF SINGLE ELECTRON TRANSISTORS

The present paper discusses the investigation of electronic properties of anthracene-based single electron transistor (SET) operating in coulomb blockade region using Density Functional Theory (DFT) based Atomistix toolkit-Virtual nanolab. The charging energies of anthracene molecule in isolated as well as electrostatic SET environments have been calculated for analyzing the stability of the molecule for different charge states. Study also includes the analysis of SET conductance dependence on source/drain and gate potentials in reference to the charge stability diagram. Our computed charging energies for anthracene in isolated environment are in good agreement with the experimental values and the proposed anthracene SET shows good switching properties in comparison to other acene series SETs.

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

The Kondo effect in a single-electron transistor

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Modern techniques of lithography make it possible to confine electrons to sufficiently small dimensions that the quantization of both their charge and their energy are easily observable. When such confined electrons are allowed to tunnel to metallic leads a single electron transistor (SET) is created. This transistor turns on and off again every time one electron is added to the isolated region. Whereas we can understand conventional transistors using classical concepts, the SET is quantum mechanical in an essential way. In fact, there is a close analogy between the confined electrons inside an SET and an atom. In this review, the physics underlying the operation of SETs is explained, a brief history of its invention is presented, and issues of current interest are discussed.

In this paper theoretical concepts based on analytical models for Single Electron Transistor (SET) are presented. It has been observed that the fabrication technology has reached on its limits for the MOS feature size, beyond which further scaling of the channel is not achievable. Due to which SET is considered as the future of the complex IC fabrication by replacing MOS technology, having small quantum dot or island, instead of channel. Working of the SET is based on the Coulomb blockade principle which is the heart of the technology. Quantum mechanics is the physics used for explaining the tunnelling of single electron of SET, which says that the energy levels are quantized not continuous. Main reason behind the advancement in SET is the market requirement of the low power, high density and fast switching devices. These are possible by SET; no doubt speed is an issue for the memories designed with SET, with its low gain and high input impedance. In the review, mathematical model including tunnelling effect in junction, coulomb blockade, current equation, free energy equation based on Shcrodinger's wave equation are presented.

The present paper discusses charge stability and conductance analyses of benzene- and zigzag graphene fragment-based single-electron transistors (SETs) operating in the Coulomb blockade regime. Graphene and benzene are modeled using density functional theory-based ab initio analyses, treating the interaction between graphene/benzene and the SET environment self-consistently. The devices consist of an oriented graphene/benzene island coupled with source and drain electrodes. The charging energy as a function of the external gate potential has been analyzed to verify the dependence of the charge stability and conductance of the oriented SETs on the source/drain bias and gate potential. Comparative analysis of these models shows that the SET with vertically oriented graphene is more stable and has better conductance in comparison with the benzene-based SET.

Recent modern fabrication technology allows us for the fabrication of nanometer-scaled devices, which is possible to observe single electronic or single electron tunneling phenomena (Averin & Likharev, 1991; Likharev, 1988; Likharev, 1999; Hanna et al., 1991; Tucker, 1992). On the other hand, MOSFET (metal-oxide-semiconductor field effect transistor) devices with channel length below 20 nanometer (nm) are no more properly operated because the downscaling of MOS devices causes a large statistical fluctuation of the threshold voltage. A possible approach to overcome this problem is to use the single electron devices for future VLSI (very large scale integrated circuit) (Takahashi et al., 1995; Saitoh et al., 2001). Nanometer scale single electron devices have the following features, i.e., low power consumption and small size. These are key features to realize ultra high density circuits. Single electron circuits with new architecture are also possible because the basic operation of single electron devices is quite different from that of conventional semiconductor devices. There are two major requirements for single electron tunneling phenomena (Coulomb blockade) to occur (Averin & Lhikarev, 1991; Likharev, 1988; Likharev, 1999). Firstly, thermal energy 倦喋劇 must be much smaller than elemental charging energy 結態 に系 ⁄ . This ensures that the transport of charges is in fact governed by the Coulomb charging energy. This condition can be fulfilled either by lowering the temperature or by decreasing the capacitance which means to reduce the island size. Usually, experiments are performed at temperatures of a few mK and for structures with island sizes of a few hundred nanometers. Second requirement is related to tunnel resistance which must exceed the quantum resistance (h ね結態 ⁄ ≈ は.の kΩ). This condition ensures that the wave functions of excess electrons between the barriers are basically localized. On the other word, in the case of lower tunnel resistance, excess charges extend over the barriers so that no single electron tunneling event can be possible. There are several types of circuits where the single electron tunneling phenomena are being explored, such as single electron box (Likharev, 1999), single electron transistor (SET) (Tucker, 1992; Takahashi et al., 1995; Saitoh et al., 2001; Wolf et al., 2010; Sun et al., 2011; Lee et al., 2009), single electron pump (Ono et al., 2003), single electron turnstile (Moraru et al., 2011) and single electron circuits with several junctions (1D and 2D arrays) (Nuryadi et al., 2003; Nuryadi et al., 2005). A double junction system is most important single electron circuit because of a basic component of SET. At small applied voltage, the system remains in the Coulomb blockade state, and no current flows through the double junctions. On the other hand, at higher applied

Electrons in a single electron transistor (SET) are transported one by one from source to drain based on the coulomb blockade mechanism. The transport rate is sensitively influenced by the presence of event a single electron charge located near the quantum dot. Based on this characteristic, we propose a Double Quantum Dot (DQD) SET to manipulate the presence of an electron in Quantum Dot (QD) as an implementation of a single-electron logic concept. The existence of an electron in the QD is used to represent logic 0 (no electron in QD) or logic 1 (an electron in QD). The logic states are sensed by a SET charge detector. Design of circuit based on DQD and SET charge detector are simulated by using SIMON 2.0 software. From the simulation, we have successfully developed a two-bit logic circuit by controlling the presence of an electron in DQD. We found that the existence of an electron in QD can be controlled by application of a gate voltage larger than 190µV. Gate should be separated from QD by a nontunnel capacitor of 500 aF. No larger than 1 aF of interdot tunnel capacitance is required to isolate the QD from one to another. The existence of an electron in QD is successfully detected by SET based charge detector.

We show the control of a charging energy in chemically assembled nanoparticle single-electron transistors (SETs) by altering the core diameter of Au nanoparticles. The charging energy is a fundamental parameter that decides the operating temperature of SETs. Practical application of SETs requires us to regulate the value of the charging energy by tuning the diameter of quantum dots. In this study, we used 3.0, 5.0 and 6.2 nm diameter synthesized Au nanoparticles as a quantum dot in the SETs. The total capacitances and charging energy of the SETs were evaluated from the rhombic Coulomb diamonds attributed to a single Coulomb island. The capacitance and charging energy matched with a concentric sphere model much better than with a simple sphere model. The operating temperatures of the SETs suggested that a charging energy 2.2 times greater than the thermal energy was required for stable operation, in theory. These results will help us to select an appropriate core diameter for the Au nanoparticles in practical SETs.

Preface V. Chandrasekhar, et al. Introduction N.O. Birge, et al. Finite Size Effects in Kondo Alloys. Effect of Disorder on the Kondo Behavior of Thin Cu(Mn) Films T.M. Jacobs, N. Giordano. The Kondo Effect and Weak Localization P. Phillips, I. Martin. Surface Magnetic Anisotropy of Kondo Impurities Induced by Spin-Orbit Scattering O. Ujsaghy. Finite Size Effects in Spin Glass Alloys. Thermopower of Mesoscopic Spin Glasses C. Strunk, et al. Shape-Induced Magnetic Anisotropy in Dilute Magnetic Alloys V.N. Gladilin, et al. Zero-Bias Transport Anomaly in Metallic Nanobridges H.B. Weber, et al. Conductance Noise and Irreversibility in Diluted Magnetic Semiconductors J. Jaroszynski, et al. Point Contact Spectroscopy and Tunnelling Spectroscopy of Kondo Impurities. Enhancement of Kondo Temperature in Nanometer-Size Point Contacts I.K. Yanson, et al. Scanning Tunnelling Spectroscopy of a Single Kondo Impurity R. Berndt, W.-D. Schneider. Two-Level Systems and Dephasing in Thin Metal Structures. Two-Channel Kondo Effect from Tunneling Impurities G. Zarand. Electron Decoherence at Zero Temperature P. Mohanty. Probing Interactions in Mesoscopic Gold Wires F. Pierre, et al. Kondo Effect in Non-Equilibrium J. Kroha. Kondo Effect in Quantum Dots. Tunneling Through a Quantum Dot A. Schiller. Electron Transport Through Quantum Dots: An Unusual Kondo Effect S. De Franceschi, et al. The Kondo Effect in a Single-Electron Transistor D. Goldhaber-Gordon, et al. Contributions Related to Poster Presentations. Flux Dependent Dielectric Response of Stacked Nanoscopic Rings K.-H. Ahn, P. Fulde.High-Frequency Response of Two-Level Systems in NixNb1-x Metallic Point Contacts O.P. Balkashin, et al. Giant Magnetoresistance of a Single Interface J. Balogh, et al. Fermi Edge Singularities in Transport Through Quantum Dots E. Bascones, et al. Theory of Magnetoresistance in Films of Dilute Magnetic Alloys L. Borda. Current and Shot Noise in a Ferromagnetic Double Tunnel Junction with an Atomic Size Spacer B.R. Bulka, et al. Positive Domain-Wall Magnetoresistance of Ferromagnetic Point Contacts J. Caro, et al. Enhancement of Kondo Effect Due to Spin-Singlet-Triplet Competition in Quantum Dots M. Eto, Y.V. Nazarov. Diagrammatic Theory of the Anderson Impurity Mod with Finite Coulomb Interaction K. Haule, et al. Generalized Conductance Sum Rule in Atomic Break Junctions S. Kirchner, et al. Is CeNiSn a Kondo Semiconductor? Y.G. Naidyuk, et al. The Influence of Single Magnetic Impurities on the Conductance of Quantum Microconstrictions A. Namiranian, et al. 7 Additional Chapters.

Single electron transistors (SETs) has been proposed as a future basis for nanoelectric components. SETs, which utilize Coulomb blockade effect arising from the electrostatic charging energy of a single electron, are one of the promising candidates for future integrated circuits due to their extremely low power consumption and high-density integration. Here, we report on the study of the formation mechanism of a nanometer-scale Au chain on a patterned SiO 2 based wafer by controlling the reaction of raw materials to form citrate Au sol and aminosilane/dithiol treated SiO 2/ Si wafer. Three gold colloidal particles (~15 nm) were aligned in a chain to form a one-dimensional current path which was bridged on a 80 nm gap between source and drain metal electrode. The SET device exhibited a Coulomb blockade effect at 40 K.

We present the perspective of CMOS electronics as a candidate for the readout purposes of sensing devices such as the Single Electron Transistor (SET) at very low temperature. Fully Depleted Silicon on Insulator (FD-SOI) CMOS devices are less susceptible to low temperature anomalies compared to bulk devices. The electrical characteristics of a typical SET are too small in comparison to usual current/voltage levels for MOS circuits and thus imposes new complications in circuit design. We present a digital readout scheme of the SET best suited for scalable design. The circuit is implemented with commercial 0.5µm SOI CMOS process operating at 4.2K. The simulation results show successful detection of 200pA drain current of an SET biased at 10µV with 15µs detection speed and static power dissipation less than 45µW.

Single electron transistor fabricated with SOI wafer

This paper demonstrates a CMOS Single electron transistor (SET) hybrid arbiter circuit which will act like a communication switch between multiple resources. The proposed architecture combines the merits of CMOS and SET to give a more efficient and compact nanometer scale circuit. The designed arbiter circuit utilizes the Coulomb blockade oscillation characteristics of SET to give better performances in terms of circuit area, power dissipation and delay. MIB compact model and BSIM4.6 model is used to design the circuit and the functionality of the result is verified by Tanner spice simulator.