The Sustained Oscillation Modeling and Its Quantitative Suppression Methodology for GaN Devices

Gallium nitride (GaN) devices are suitable for high-frequency power converters due to their excellent switching performance. To maximize the performance of GaN devices, it is necessary to study the switching characteristics, which requires measuring the switching current. However, GaN devices have a fast switching speed and are sensitive to parasitic parameters, so the current measurement should have a high bandwidth and should not introduce excessive parasitic inductance into the power converters. Traditional current measurements are difficult to meet these requirements, especially for fast GaN devices. This paper presents a high-bandwidth integrated current measurement for detecting the switching current of fast GaN devices. By effectively utilizing the parasitic inductance in the circuit, a single-turn coil is embedded in the printed circuit board. This coil could pick up a sufficiently strong voltage signal, which is then processed to reconstruct the switching current. Moreover, corrections are carried out to further improve the accuracy. The current measurement has a small insertion impedance and a high bandwidth with a small influence on the parasitic inductance of the converter. The accuracy of the current measurement is experimentally verified by a 40 V GaN-based double pulse test circuit with a load current up to 25 A.

The high frequency capability and low on-state losses of Gallium Nitride (GaN) transistors offer the potential to increase converter efficiency and/or reduce heatsink and passive component size. This paper investigates the use of GaN technology to enhance the performance of power factor correction (PFC) and LLC converters for battery charging applications. First the efficiency performance of non-isolated PFC converters using GaN transistors is compared by simulation, the asymmetric bridgeless PFC converter is shown to achieve the best efficiency, with a predicted figure of 99% in a 1MHz, 200W design. The predictions are validated by an experimental prototype using a GS66502B, GaN Systems E-mode GaN transistor. Then the efficiency comparison of the PFC and LLC converter using GaN devices for battery charging applications is included in the paper. The experimental results of the PFC converter with GaN devices are also included. Additionally, this paper includes the analysis and design of a common mode input filter for the GaN-based high frequency converters for battery charging application. The size of both the converters using GaN devices is reduced by 40% than the converters based on Si devices. The switching loss comparison of GaN and Si devices are also included in the paper.

Gallium Nitride (GaN) and Silicon Carbide (SiC) power devices are segmented in the Wide Bandgap (WBG) device market: GaN devices are suitable for high-frequency but low-voltage applications; SiC devices are suitable for low-frequency but high-voltage applications. Cascoding a GaN HEMT and a SiC JFET best utilizes the advantages of both of these WBG power devices. Like GaN devices, the cascode GaN/SiC device is easy to drive at high frequencies and has low gate loss; like SiC devices, it also has relatively high voltage rating and low C oss energy loss at high frequencies. In previous studies, power circuits using the cascode device achieved higher power density than circuits using only a SiC device but efficiency similar to that of a SiC device [1]. In this paper, we present our investigation of the gate loss mechanism of the SiC JFET in the cascode structure and our finding that the loss can be greatly reduced by minimizing the gate resistance of the SiC JFET (R g,Jfet ). Simulation results showed that reducing R g,Jfet from 6 Ω to 1 Ω at 13.56 MHz leads to a 5× loss reduction, and experimental data verified the simulation trend. Here we provide a simple guideline to optimize the cascode GaN/SiC device and achieve better performance in high-frequency and high-voltage applications.

This paper will revise, experimentally investigate, and discuss the main application challenges related to gallium nitride power semiconductors in switch-mode power converters. Gallium Nitride (GaN) devices are inherently gaining space in the market. Due to its high switching speed and operational switching frequency, challenges related to the circuit design procedure, passive component selection, thermal management, and experimental testing are currently faced by power electronics engineers. Therefore, the focus of this paper is on low-voltage (<650 V) devices that are used to assemble DC-DC and/or DC-AC converters to, for instance, interconnect PV generation systems in the DC and/or AC grids. The current subjects will be discussed herein: GaN device structure, the advantages and disadvantages of each lateral gallium nitride technology available, design challenges related to electrical layout and thermal management, overvoltages and its implications in the driver signal, and finally, a comprehensive comparison between GaN and Si technology considering the main parameters to increase the converters efficiency.

This paper presents the analysis and design of gallium nitride (GaN) devices based flyback converter. It is critical to optimize power loop and gate loop for flyback converter due to high dv/dt of GaN device. EPC devices with 200V/12A were used in flyback converter. Because GaN device has no avalanche voltage and is sensitive to gate voltage, one need pay more attention to design of gate driver and selection snubber circuits. Different snubber circuits for GaN based flyback converter were compared in this paper. Magnetics selection for high frequency (HF) transformer was discussed in view of size, frequency, turn ratio and loss. A detailed power loss breakdown has been executed with core loss, cooper loss, leakage inductance loss, conduction loss and switching loss. Performance, such as current/voltage stress, voltage spike, efficiency, ect., were analyzed and compared under continuous conduction mode (CCM), boundary conduction mode (BCM), discontinuous conduction mode (DCM), and BCM with valley switching. Experimental results show highest efficiency is achieved under BCM with valley switching.

Gallium nitride (GaN) devices show particular promise for space-rated power conversion applications that rely on MOSFET technology whose performance is severely limited by the radiation hardening processes. Although the number of radiation-hardened (rad-hard) GaN devices is low, the current space-rated selection pool can still yield significant efficiency and power density improvements. However, the context of GaN research is often future-oriented such that the application of GaN to common, proven, space-rated converter designs is rare. The presented work quantifies the performance benefits of market available, space-rated GaN HEMTs over rad-hard MOSFETs for a synchronous forward converter, which remains an extremely popular topology for isolated, medium-power, dc–dc conversion on various satellite systems. Two 75-W, space-rated forward converters were designed, implemented, and benchmarked, with the power switch technology being the single variable of change. By forming Pareto-optimal fronts of the key device metrics, optimal rad-hard MOSFETs were chosen so that the baseline converter performance was considered the best case. The frequency limitations of common, available, rad-hard PWM controllers limited the power density in the GaN and Si converters alike; however, efficiency gains proved sizeable. The GaN-based converter saw a peak efficiency of 86%, which was a 4.54% improvement over the Si baseline. Detailed efficiency and loss differential plots are presented, which show the GaN converter’s reduced sensitivity to the input voltage.

The load cycling capability of novel power semiconductors is an important aspect when estimating their lifetime in field service. The Power Cycling Test (PCT) is the standard test to evaluate the lifetime of a semiconductor device under thermo-mechanical stress. PCTs are typically performed at temperature swings (ΔT) much higher than common operating conditions, to obtain results within a reasonable time. In this work, the PCT capability of gallium nitride (GaN) and gallium oxide (Ga2O3) lateral transistors is investigated. The GaN devices were tested in two groups with different ΔT. The temperature of the devices was monitored using two different temperature sensitive electrical parameters (TSEPs) and the accuracy of both methods was evaluated by comparing the results with the temperature, monitored by using an infrared (IR) camera. For Ga2O3 devices, no data on potential TSEP exists so far, thus, the typical TSEP for silicon (Si), silicon carbide (SiC) and GaN were investigated for their applicability to Ga2O3 devices. While a PCT was conducted on the devices, the temperature was also monitored using an IR camera. The results of the comparison of TSEP and IR camera data showed, that the accuracy of the TSEP for GaN matched either the temperature of the hottest spot on the chip (VDS method), or the average chip temperature (VGS method). For the Ga2O3 devices no suitable TSEP could be obtained and only the IR camera was used for the temperature measurement. It revealed a very uneven temperature and thus, current distribution on the chip. Furthermore, both GaN and Ga2O3 devices exhibit an outstanding power cycling capability with no failure after completing several millions of cycles. Considering the difference in Young’s Modulus of Si, GaN and Ga2O3, the PCT performance of GaN on silicon devices and Ga2O3 devices should be inferior to silicon devices. Thus, both device types, the GaN transistors and the Ga2O3 transistors, showed a PCT capability much higher than expected.

Dynamic ON-resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}{)}$ </tex-math></inline-formula> or threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}{)}$ </tex-math></inline-formula> instability caused by charge trapping is one of the most crucial reliability concerns of some gallium nitride (GaN) high-electron mobility transistors (HEMTs). It has been unclear if this issue can be resolved using an alternative GaN device architecture. This work answers this question by characterizing, for the first time, the dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{\text {ON}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> stability of an industrial vertical GaN transistor-NexGen’s 1200-V/70- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> fin-channel junction-gate field-effect transistor (JFET), fabricated on 100-mm bulk GaN substrates. A circuit setup is deployed for the in situ measurement of the dynamic <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> under steady-state switching. The longer term stability of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> is tested under the prolonged stress of negative gate bias and high drain bias. The vertical GaN JFET shows nearly no <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{\text {on}}$ </tex-math></inline-formula> or <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift in these tests, which could be attributed to the low defect density of the GaN-on-GaN homoepitaxial growth, the absence of electric field ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}$ </tex-math></inline-formula> -field) crowding near the surface, and the minimal charge trapping in the native junction gate. These results present a critical milestone for vertical GaN devices toward power electronics applications.

To address the accuracy limitations of the traditional double pulse test (DPT) for measuring switching losses in high-speed gallium nitride (GaN) devices and the slow measurement speed of conventional calorimetric methods, this paper proposes a fast and accurate calorimetric-based method for characterizing GaN switching losses. Compared to DPT, this method allows rapid and faithful measurement of switching losses under both soft- and hard-switching conditions. A testing measurement platform was developed, which confirmed that this method can collect temperature data in 5 minutes or less by characterizing the switching losses of top-side cooled GaN devices. Achieve a measurement error of less than 9% compared to DPT. It can be used as a supplementary method to verify the accuracy of DPT. The combination of the two methods can achieve cross-validation, significantly improving the reliability of GaN device switching loss measurement results.

Understanding the cryogenic performance of Gal-lium Nitride (GaN) devices is essential for determining their suitability for use in the electrification of large-scale transport such as aircraft, where the power electronics may need to withstand cryogenic temperatures. In this paper we investigate the temperature relationship of the channel on-resistance and gate threshold voltage of various GaN devices, using liquid nitrogen as an inexpensive and effective cryogenic medium. Two cascode-configuration high electron mobility transistors (Cascode HEMT) and two enhancement mode high electron mobility transistors (E-HEMT) devices, each from different manufacturers were selected to ensure a range of technologies were covered. The on-resistance of GaN devices was found to decrease approximately linearly with reducing temperature, until a knee-point is reached whereupon the on-resistance rises. One E-HEMT device did not reach a knee point, indicating the need for further testing at lower temperatures to determine whether, or where such a knee point exists. The device with the lowest normalised on resistance at -196.6°C exhibited 32.8% of its room temperature value, while the device with the highest normalised on resistance showed 89.3% of its room temperature value. It was also found that the gate thresh-old voltage shows temperature dependency. For both Cascode manufacturers, the threshold voltage increased linearly with decreasing temperature. For one of the E-HEMTs the threshold voltage increased non-linearly with decreasing temperature. For the other E-HEMTs the threshold voltage decreased linearly with decreasing temperature. Initial results indicate that GaN devices are compatible with operation in or near cryogenic environments. Further characteristics need investigation to fully confirm suitability. Output characteristics, as well switching rise and fall times may change in cryogenic conditions, potentially affecting suitability.

Compared with Si devices, wide bandgap (WBG) devices will cause more serious electromagnetic interference (EMI) problems due to their fast switching speeds. In order to better compare and predict their EMI, this article proposes an improved mathematical modeling method to calculate the EMI spectrum envelope. It is based on an accurate time-domain decomposition of switching transient behavior together with a frequency-domain calculation. Detailed EMI spectrum envelope analytic expressions are derived with full consideration of Miller platform (MP), reverse conduction (RC), and ringing effects, while traditional calculation mainly focused on <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">du/dt</i> . The proposed mathematical modeling method has been applied to Si, silicon carbide (SiC), and gallium nitride (GaN) devices, respectively, and verified by comparing calculated and simulated results. In order to further verify this method, double-pulse test circuits of Si, SiC, emode GaN, and cascade GaN are built, and CM and DM EMI are also compared. The result reveals that, compared with Si devices, the MP, RC, and ringing effects of WBG devices have more serious effects on EMI.

The voltage rating of the commercial Gallium Nitride (GaN) power devices are limited to 600/650 V due to the lateral structure. Stacking the low-voltage rating devices is a straightforward approach to block higher dc link voltage. However, the unbalanced voltage sharing can occur due to the discrepancies in the gate driving loops, the device parameter tolerance and the device-to-ground displacement currents for the series-connected devices in the stack. The voltage imbalance may cause the over-voltage breakdown, in particular for GaN devices, which do not have the avalanche breakdown mechanism. In this article, a novel controllable current source gate driver is proposed, which addresses the voltage imbalance issue of series-connected GaN HEMTs for both hard switching and soft switching scenarios. The proposed current source gate driver controls the device switching timing and the dv/dt with fine accuracy by directly regulating the device gate current. Without the employment of the lossy snubber circuit or the external Miller capacitor, the switching energy and the switching speed are almost not compromised for each individual device. Meanwhile, the current mirror circuits are utilized as the discontinuous pulsed current sources, which produce negligible additional gate driving loss. A series-connected GaN-based multiple pulse tester is built to validate the proposed current source gate driver and the voltage balancing strategies. It is demonstrated that the drain-to-source voltage difference of the series-connected GaN devices is below 10% for different load current and different switching speed (dv/dt) conditions. Moreover, it is found that the series-connected GaN solution can save 33.6% switching energy compared with the benchmark SiC solution under the same operating condition.

Recently, multilevel converters with gallium nitride (GaN) devices have shown marvelous advantages for power factor correction (PFC) conversion to meet the increasingly higher efficiency and power density requirements. In the traditional design process for the multilevel PFC converter, it is necessary to separately optimize the devices of the corresponding breakdown voltage under different level number, which causes difficulty to the overall optimization of the entire system. In this paper, a unified minimum loss model for GaN switches regardless of voltage levels is proposed to optimize the efficiency based on device’s new figure-of-merit (NFoM) (NFoM = COSS(ER) RDS(on)). With the help of this unified minimum loss model, it simplifies the efficiency optimizing methodology according to the NFoMs of GaN devices for multilevel PFC converter. According to the methodology, a 2 kW cascaded H-bridge (CHB) PFC prototype is constructed to verify the design methodology, achieving over 99% efficiency with power density over 1000 W/in3 .

In various industrial applications, including aviation, electric vehicles, and drilling, the demand for semiconductor devices and associated circuits with high thermal stability is progressively increasing. Wide-bandgap semiconductor Gallium Nitride (GaN) devices exhibit the advantages of fast switching capability, low on-resistance, and the ability to operate at high temperatures. These advantages have made them potential candidates for integrated circuits in high-temperature environments in recent years. Lateral GaN devices promote monolithic integration, which consequently increases power density and reduces cost of cooling systems. Hence, it is worthwhile to investigate the performance of GaN devices in high-temperature environments. This review aims to present a thorough review of high-temperature characteristics of GaN devices and integrated circuits. The performance of GaN devices at high temperatures, such as threshold voltage，saturation current and on-resistance, has been reviewed in response to different structures. The underlying degradation mechanisms related to the intrinsic properties of structures and fabrication technology are discussed at high temperatures. The thermal performance of GaN small signal integrated circuits and power converters was presented. This paper systematically examines the advantages and challenges of GaN devices and integrated circuits at high temperature environments.

SiC MOSFET is fast switching, high voltage blocking and current carrying, and low loss device is much closer to ideal switch. Therefore, SiC MOSFETs applications are high power density matrix converter, battery charger in electric vehicles, and others. The matrix converter is built on bidirectional switches, which allow both positive and negative current and block both positive and negative voltage. The SiC MOSFET based bidirectional switches are more prone to the detrimental effect of power supply line inductance due to their very high switching speed. The very high rate of current change with time during turn OFF may damage the switch due to overvoltage across it. The conventional methods to reduce this effect are decoupling capacitance and RC snubber. The decoupling capacitance method reduces the overvoltage across the switch for small line inductances, does not slow down the switching speed, and is easier to implement compared to the RC snubber method but increases the radiated electromagnetic interference. However, these methods are not studied for SiC MOSFET based bidirectional switches. Therefore, this paper compares the two methods for SiC MOSFET based bidirectional switch with the help of time domain analysis, simulation, and experimental results. The comparison shows that sustained oscillations in switch voltage exist with decoupling capacitance and is absent with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$RC$</tex> snubber.