The use of a test specification format in automatic test program generation

A novel environment for test program development will be introduced that supports automatic specification-driven and computer-assisted test parameter acquisition, automatic test program generation and automatic documentation generation. Test parameter and test pattern acquisition, main portion of test program generation and documentation generation have been designed to be tester-independent by means of automatic technology file access and simulation-to-test signal conversion. A built-in rule checker guarantees for test parameter consistency and completeness. Runtimeoptimization of test programs, and test document generation can be done upon user request.

: The objective of the research is to design an automation aid for generating test programs that will (1) reduce the required user expertise, (2) reduce labor, (3) enhance efficiency, (4) improve user confidence, and (5) provide documentation for furture utilization and maintenance. The report presents a test description language, NOPAL, in which a user may describe diagnostic tests, and a software system which automatically generates test programs for an automatic test equipment based on the descriptions of tests. The software system accepts as input the tests specified in NOPAL, performs syntax analysis, and constructs a directed graph. Based on the graph the system proceeds to check for consistency, completeness, and unambiguity in the supplied descriptions. The execution sequence of the tests is then optimized. Finally, an efficient program in a test equipment programming language, OPAL, is generated. (Author)

An algorithm called the O-algorithm is introduced for automatic test program generation of microprocessors in a user environment. To eliminate redundant tests, a weight-digraph model is used to model the signal flow of the general microprocessors. Improved functional fault models of microprocessors are derived from the Turing machine model. The O-algorithm is then constructed on the basis of the signal flow model and functional fault models. Simulation has shown that the fault coverage is better than 97%.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The paper develops a methodology for the automatic test program generation (ATPG) for a large analogue circuit subject to component drifts. An optimization algorithm developed selects the best set of intermediate access points for a.c. and d.c. tests of the circuit.During ATPG, faults are simulated by varying each component over a wide range. Voltages measured at all available nodes are thus used in the pre-processing stage of node selection. An optimization procedure based on the discriminating power of measurements and separability between fault signatures is used to select the best set of frequencies applicable for all nodes in a.c. testing. A preamplifier and control amplifier of 56 components is chosen as Unit Under Test (UUT) to demonstrate the ATPG. The fault isolation scheme used is based on the nearest neighbour rule.The rexlationship between diagnosability and number of test features is shown to follow the customary Pareto type curve. However, four carefully chosen nodes and three carefully chosen test frequencies are shown to give an adequate level of diagnosability. The whole scheme is implemented automatically using a minicomputer interfaced to the UUT.

While the performance, density, and complexity of application-specific systems increase at a rapid pace, equivalent advances are not being made in making them more easily testable, diagnosable, and maintainable. Even though testability bus standards, like JTAG Boundary Scan, have been developed to help eliminate these costs, there exists a need for efficient hardware and software tools to support them. Hence, a testability design and hardware support environment for application-specific systems is described which provides a designer with a set of hardware modules and circuitry, that support these standards and software tools for automatic incorporation of testability hardware, as well as automatic test vector and test program generation.

This paper presents new techniques in two different areas. Firstly, it proposes a solution to the problem of testing embedded processors. Towards this end, it discusses the automatic generation of executable test programs from a specification of test patterns for processor components. Secondly, the paper shows how constraint logic programming (CLP) improves the software production process for design automation tools. The advantages of CLP languages include: built-in symbolic variables and the built-in support for constraints over finite domains such as integers and Booleans.

Chapter 3 - Mimola—A Fully Synthesizable Language

This paper introduces a new method for manually generating test programs to validate a processor design. Current manual methods do not utilize high level of abstraction for describing test programs and lack many important features like reusability, incremental validation, and test program compaction; they also work on a formal model specifically developed for validation purposes. To solve the above problems, we use test specification expressions to describe test programs and generate test sequences based on an instruction-set description of a processor written for synthesis purposes. We provide experimental results of generating test programs for several processors to show the effectiveness of our method.

With the evolution of casing drilling technology, connections are subjected to increasingly stringent well conditions. These conditions include higher pressures, higher temperatures, and higher mechanical loads for longer drilling periods. As a result, the performance of the connector under these conditions is of increasing concern. Most recent casing connection evaluation test programs are based on ISO 136791 requirements. However, API RP72 is the dominant testing program for drill stem applications. Drilling with casing applications combine drilling and casing concerns. As a result, a new test program is required to adequately characterize connection performance when used in casing drilling applications3. As part of the test program, the static and dynamic connector capacities are individually evaluated to benchmark the design. Based on these results, additional testing is conducted todetermine the connector static capacity after dynamic loading for an expected drilling period at an expected maximum build rate. This testing demonstrates the connector performance under drilling with casing application conditions. This testing program may be utilized to better define connector performance limits when used in drilling with casing applications leading to increased operational safety and lower overall risks. A better understanding of how connection tolerances impact connection performance under combinations of static and dynamic loading conditions will aid in connector selection for drilling with casing applications and may allow the technology to be used in broader applications. The paper includes results, observations, and conclusions from a subject test per the testing program. The subject test is currently being conducted on a 9-5/8" 53.50ppf P-110 drilling with casing connector. Introduction The objective of this project is to evaluate the connection performance for casing drilling application. Tests were conducted in four phases, each with distinctive goals.Phase I: Design SelectionPhase II: Fatigue to Failure TestPhase III: Static Capacity TestPhase IV: Post-fatigue ISO Series B Test The objective of Phase I test was to find the best connection and thread compound combination. Three samples with different thread compounds were tested. DWC/C and DWC/C-SR connections were fatigue tested with the same loading condition. All samples were threaded to nominal tolerances and subsequent capped-end pressure test determined the best design for Phase II test. Phase II was to generate the SN curve for DWC/C-SR connection. Three ISO configurations, with three samples in each group, were tested at different stress levels. Connections were fatigued to failure with different stress range. Fatigue performance with respect to sample configuration was investigated. ISO 2 configuration is the worst-case for fatigue. Phase III was the static capacity verification test. Three ISO configurations, identical as tested in Phase II, were tested with ISO Series B service load envelope (SLE). The configuration with the best pressure containability was chosen for Phase IV test. Phase IV included the post-fatigue ISO Series B test. The specimens were fatigued to pre-determined cycles at a certain stress level, followed by an ISO Series B testing. The testing format was modified based on ISO 13679 requirement.

Quantifying the benefit of a developmental test program: Probabilistic Risk Assessment and Red Bull Stratos

The continuous advances in microelectronics design are creating a significant challenge to design validation in general, but tackling piplined microprocessors is remarkably more demanding. This paper presents a methodology to automatically induce a test program for a microprocessor maximizing a given verification metric. The approach exploits a new evolutionary algorithm, close to Genetic Programming, able to cultivate effective assembly-language programs. The proposed methodology was used to verify the DLX/pII, an open-source processor with a 5-stage pipeline. Code-coverage was adopted in the paper, since it can be considered the required starting point for any simulation-based functional verification processes. Experimental results clearly show the effectiveness of the approach.

Test program generation and simulation is the most widely used approach to functional verification of microprocessors. High complexity of modern hardware designs creates a demand for automated tools that are able to generate test programs covering non-trivial situations in microprocessor functioning. The majority of such tools use test program templates that describe scenarios to be covered in an abstract way. This provides verification engineers with a flexible way to describe a wide range of test generation tasks with minimum effort. Test program templates are developed in special domain-specific languages. These languages must fulfill the following requirements: (1) be simple enough to be used by verification engineers with no sufficient programming skills; (2) be applicable to various microprocessor architectures and (3) be easy to extend with facilities for describing new types of test generation tasks. The present work discusses the test program template description language used in the reconfigurable and extensible test program generation framework MicroTESK being developed at ISP RAS. It is a flexible Ruby-based domain-specific language that allows describing a wide range of test generation tasks in terms of hardware abstractions. The tool and the language have been applied in industrial projects dedicated to verification of MIPS and ARM microprocessors.

Software-based Self-test (SBST) is one of the techniques adopted to detect latent faults in safety-critical applications, thus aiming at preventing them from producing failures. When adopted for in-field test, not only the achieved fault coverage, but also the test duration of SBST test programs become critical parameters. Sometimes, these test programs are created following guidelines allowing to guarantee a given Fault Coverage with reduced test duration. In other cases, existing test programs are re-used. Hence, it is important to devise automatic techniques able to modify them in such a way that the fault coverage is kept unchanged (or increased) while the test duration is reduced. This paper presents a possible approach in this direction. Its effectiveness is evaluated on some test programs targeting the openMSP430 processor. Experimental results show that the proposed method is able not only to significantly reduce the test duration (up to 26%), but also to further increase the achieved Fault Coverage, while keeping the required computational time acceptable.

Most Systems-on-a-Chips include a custom microprocessor core, and time and resource constraints make the design of such devices a challenging task. This paper presents a simulation-based methodology for the automatic completion and refinement of verification test sets. The approach extends the µGP, an evolutionary test program generator, with the possibility to enhance existing test sets. Already devised test programs are not merely included in the new set, but assimilated and used as a starting point for a new test-program cultivation task. Reusing existing material cuts down the time required to generate a verification test set during the microprocessor design. Experimental results are reported on a small pipelined microprocessor, and show the effectiveness of the approach. Additionally, the use of the proposed methodology enabled to experimentally analyze the relationship of the different code coverage metrics used in the test program generation.

Grammatical Evolution generates computer programs automatically in any arbitrary language using Backus-Naur Form of Context-free Grammar in automatic programming. Variable-length Genetic Algorithm is used as a learning algorithm in Grammatical Evolution. Fireworks algorithm is a recently developed new Swarm Intelligent algorithm used for function optimization. This paper proposes Grammatical Fireworks algorithm which uses Fireworks algorithm as a learning algorithm in place of variable-length Genetic Algorithm in Grammatical Evolution to evolve computer programs automatically. Grammatical Fireworks algorithm is applied on three well-known benchmark problems such as Santa Fe ant trail, symbolic regression and 3-input multiplexer problems. A comparative study is made with Grammatical Evolution, Grammatical Swarm, Grammatical Artificial Bee Colony, and Grammatical Differential Evolution. The experimental results demonstrate that the proposed Grammatical Fireworks algorithm can be applied in automatic computer program generation.