ThermalScope: Multi-Scale Thermal Analysis for Nanometer-Scale Integrated Circuits

Praise for Signal Integrity Effects in Custom IC and ASIC Designs For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. --Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip. --Kenneth L. Shepard, Professor, Columbia University book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity. --Jake Buurma, Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc. collection of papers...is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection. --Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley The editor has gathered together a collection of papers, both tutorial and advanced, that address a broad range of interconnect problems. --Jacob White, Professor, Massachusetts Institute of Technology Signal Integrity Effects in Custom IC and ASIC Designs compiles recent expert research papers in state-of-the-art IC (Integrated Circuits) design. It offers a detailed focus on all the major topics in understanding and modeling real-world IC signal integrity issues for CAD and IC design engineers, as well as graduate engineering students. Practical, in-depth discussion of interconnect effects, inductance effects, power grid and distribution noise, and substrate noise and coupling is included. This specialized coverage provides the knowledge necessary to overcome serious problems in new, more complicated IC designs, such as:Wired and wireless communications ICs Large custom analog mixed-signal ICs ASIC designs from 0.12 microns and above Integrated custom IC blocks in ASIC (Applications-Specific Integrated Circuit) designs

In integrated circuit (IC) design for advanced manufacturing processes, iterative improvement processes are an approach commonly used for improving design quality, particularly for low-energy, high-frequency circuits. Layout-dependent effects (LDEs) affect IC design and fabrication, resulting in differences in circuit functionality and performance in presimulation versus postsimulation. These differences can greatly increase the length of design iteration cycles. Foundries have attempted to accelerate the iterative design process by providing process design kit libraries to IC designers. However, these kits can neither fully mitigate the negative affect of LDEs on design for manufacturability (DFM) nor eliminate the difference between presimulation and postsimulation results. To address this problem, this study proposed a novel algorithm-based design process in which an IC designer can use layout parasitic extraction to extract the DFM parameters of all components in a circuit prior to the routing process; these parameters include netlists that describe the internal connectivity of components as well as their interconnectivity with other components. Accordingly, the IC designer can determine the effects of DFM parameters on the circuit and modify them in advance if necessary. When the LDEs generated by device placement have been confirmed to not affect circuit properties, physical verification of the routing of metal wires in the IC layout can be performed. In this verification, postsimulations only need to focus on problems regarding the wire loading and timing effects of metal routing. The proposed design process is useful for mitigating LDEs in IC design and considerably reduces the time required for iterative improvement processes. Specifically, this study provides a method of enhancing design iteration cycles and provides guidelines for analyzing factors that hinder IC device functionality and performance. In sum, various problems can be resolved by separately extracting the DFM parameters associated with LDEs and parasitic parameters associated with routing.

Advances in interconnect technologies, such as the increase of the number of metal layers and 3-D stacking technique, have paved the way for higher functionality and superior performance while reducing size, power, and cost in today's integrated circuits and package products. With the increase of clock frequency and edge rates as well as the continuously downscaling of feature size and 3-D interconnect technologies in high-speed systems, signal integrity (SI) effects such as signal delay, reflection, attenuation, dispersion and crosstalk have become one of the dominant factors in current deep sub-micrometer CMOS technologies limiting overall performance of high-speed systems.Another major difficulty is the power integrity (PI) issue. For example, IR drop is caused by the finite resistivity (R) of metals and current (I) drawn off from the power/ground planes. Chip designs are susceptible to IR drop, especially when the integrated circuit (IC) supply voltage Vdd decreases with the scaling of silicon processes. IR drop is proportional to the resistance of the power/ground plane. When the resistance of power/ground plane increases, with the shrinking of complex geometries, the IR drops will in turn increase as well. To further confound the difficult issue, the rise of the thermal temperature due to the current carrying interconnects also has tremendous impact on the IC performance and reliability. Current flow in a VLSI interconnect can cause a power dissipation, which is referred to as Joule heating or self-heating. The Joule heating effects are becoming increasingly significant with the shrinking scale of silicon process because of the increase of on-chip power density, inclusion of more metal layers with higher densities, and the use of dielectric materials with lower thermal conductivities. Subsequently, the temperature effects on the electrical performance of 3D systems should be carefully considered as well in the electrical designs.Unfortunately, almost all practical SI and PI problems are multi-physics in nature, and various physical phenomena are usually interacting and coupling to each other. For instance, the resistivity of most conducting metals increases linearly with the increases of the surrounding temperature resulting from the Joule heating by electric currents flowing through the conductors. Therefore, in order to accurately characterize the performance of high power integrated circuits (ICs), packages and printed circuit boards (PCBs), it is essential to account for both electric and thermal effects and the intimate couplings between them.In this paper, we propose to use non-conformal, non-overlapping domain decomposition methods (DDMs) for the signal integrity analyses and thermal-aware DC IR drop co-analysis of high-power IC-Package-PCBs. The proposed DDM starts by partitioning the composite device into inhomogeneous sub-regions with temperature dependent material properties. Subsequently, each sub-domain is meshed independently according to its own characteristic features. As a result, the troublesome mesh generation task for complex ICs can be greatly subdued. Moreover, the proposed thermal-aware DC IR drop co-analysis applies the non-conformal DDMs for both conduction and steady state heat transfer analyses with a two-way coupling between them. Furthermore, we extend the non-conformal DDM to study transient thermal temperature distribution within complex ICs. Numerical examples, including an IC package and an IC-Package-PCB, demonstrate the flexibility and potentials of the proposed non-conformal DDMs for SI analyses and thermal-aware DC IR-drop co-analysis.

A survey and an analysis of the publications concerned in thermal analysis (TA) published in four renowned journals during the years 1965–1974 were performed. The published data were evaluated from three points of view: TA methods used for polymers, properties and phenomena studied by TA methods, types of polymers investigated by TA methods. From the statistical data were derived the future trends for the application of particular TA methods in polymer science.

Computer-aided design (CAD) tools play a critical role in optimizing integrated circuit (IC) designs, especially as the complexity and scale of ICs continue to grow. This paper introduces a via-aware parallel layer assignment algorithm to address the key challenges of routing and layer assignment in large-scale IC designs. The algorithm utilizes parallel processing techniques to divide the IC layout into distinct regions, improving load balancing and reducing routing congestion. Additionally, the via-aware strategy minimizes the number of vias used during layer assignment, significantly lowering manufacturing costs. Experimental data show that this method reduces runtime by approximately 22% and via count by 15% compared to traditional algorithms. Notably, when handling complex test cases, the algorithm demonstrates a substantial increase in efficiency, with a runtime speedup ratio of 2.16 and a via count reduction of 11.60% in most test cases. These results indicate that the proposed algorithm is highly effective in optimizing IC design for large-scale applications, with significant practical value.

Thermal analysis and calorimetric methods in the characterisation of polymorphs and solvates

Is the science of thermal analysis kinetics based on solid foundations?: A literature appraisal

This paper presents a detailed overview of the Micro- and Nano-electronics curriculum for Bachelor's and Master's degree studies programs in Vilnius Gediminas Technical University (VGTU). These programs focus on giving the ability and knowledge to students in designing an Integrated Circuits (ICs) using advanced EDA Tools. The Micro- and Nanoelectronics education programs cover all aspects of the IC design process: from the understanding of IC manufacturing processes and technologies to IC verification, physical design implementation and testing. Through cooperation with research institutes, industries, and governments both at home and abroad, these programs only become even stronger. These Micro- and Nano-electronics programs are designed to educate a large number of talented IC designers, to increase the number of startup companies in IC design and finally to establish a microelectronics industry ecosystem in Lithuania and in the European Union (EU).

Thermal issue is a primary concern in three-dimensional (3D) integrated circuit (IC) design. In modern IC design, leakage power is becoming a key design challenge which contributes to thermal issues. Due to technology scaling, the leakage power is rising so quickly that it largely increases the die temperature. In this paper, we first investigate the impact of leakage power on thermal profile in 3D packings, and then we analyze thermal and leakage aware floorplanning based on 3D-STAF[17] platform. Finally, the effects of thermal controls including the thermal-aware floorplanner and thermal via insertion for thermal management are analyzed in experiment results. The results show that leakage power increases the maximal temperature on the chip greatly about50%. Hence, the required thermal via number also increases greatly about 52.6%.

The number of transistors per chip, feature sizes, frequencies, transistor densities, number of cores, thermal design powers, die areas, and storage capacities of Integrated Circuits (ICs) used for different processing units and memories were collected from various websites from 1973 to 2019 and plotted against year of introduction of ICs in semi-log paper to find the trend with R-squared (R2) value using Microsoft Excel. The R2 values of the trend lines for the above parameters were over 0.922 which indicated that more than 92% of data satisfied the fitting lines except for thermal design power (R2 = 0.7) and die area (R2 = 0.4 to 0.6). It was observed that the growths of transistor counts, transistor densities, frequencies, and thermal design powers for different processing units were growing exponentially and doubled every 16.8 to 24 months from 1973 to 2019 except the growth of thermal design powers (TDP) and frequencies of ICs which were increased up to 2003. After that, the growth of TDP and frequencies are nearly linear up to the present day. The growth of the above parameters for ICs of different memories was a little faster, it was doubled every 14 to 16 months. The feature sizes shrunk 2 times every 18 months. A strong relation was found between feature sizes and transistor densities (R2 = 0.9) and observed that one fold of feature size decreased for the increasing of 2-3 folds of transistor densities. It was observed that different parameters for ICs designing from 1973 to 2019 kept pace with Moore's law. It may be concluded that the decrease of feature size, increasing of transistor count and transistor density in ICs design will follow Moore's law for some more years with the limitation of frequency and power of ICs.

The complicated steel wheel and rail interaction on curve causes side wear on rail head. Thus, the cost of maintenance for the track on curve is significantly higher than that for track on a tangent. The objective of this research is to develop 3D printing technology for repairing the side wear. In this paper, the study examines induced residual thermal stresses on a rail during the cooling down process after 3D printing procedure using the coupled finite volume and finite element method for thermal and mechanical analysis respectively. The interface of the railhead and additive materials should conserve high stresses to prevent any crack initiation. Otherwise, the additive layer would likely shear off the rail due to crack propagation at the rail/additive interface. In the numerical analysis, a cut of 75-lb ASCE (American Society of Civil Engineers) worn rail is used as a specimen, for which a three-dimensional model is developed. The applied residual stresses, as a result of temperature gradient and thermal expansion coefficient mismatch between additive and rail materials, are investigated. At the beginning, the worn rail is at room temperature while the additive part is at a high initial temperature. Then, additive materials start to flow thermal energy into the worn rail and the ambient. The thermal distribution results from thermal analysis are then employed as thermal loads in the mechanical analysis to determine the von-Mises stress distribution as the decisive component. Then, the effect of preheating on residual stress distribution is studied. In this way, the thermo-mechanical analysis is repeated with an increase in railhead’s initial temperature. In thermal analysis, the temperature contours at different time steps for both the non-preheated and preheated cases indicate that preheating presents remarkably lower temperature gradient between rail and additive part and also represents a more gradual cooling down process to allow enough time for thermal expansion mismatch alignment. In mechanical analysis, the transversal von-Mises stress distribution at rail/additive interface is developed for all cases for comparison purposes. It is shown that preheating is a key factor to significantly reduce residual stresses by about 40% at all points along transversal direction of interface.

Future space exploration missions will require the development of more advanced in‐space radiators. These radiators should be highly efficient and lightweight, deployable heat rejection systems. Typical radiators for in‐space heat mitigation commonly comprise a substantial portion of the total vehicle mass. A small mass savings of even 5–10% can greatly improve vehicle performance. The objective of this paper is to present the development of detailed tools for the analysis and design of in‐space radiators using evolutionary computation techniques. The optimality criterion is defined as a two‐dimensional radiator with a shape demonstrating the smallest mass for the greatest overall heat transfer, thus the end result is a set of highly functional radiator designs. This cross‐disciplinary work combines shape optimization and thermal analysis design by means of a genetic algorithm. The proposed design tool consists of the following steps; design parameterization based on the exterior boundary of the radiator, objective function definition (mass minimization and heat loss maximization), objective function evaluation via finite element analysis (thermal radiation analysis) and optimization based on evolutionary algorithms. The radiator design problem is defined as follows: the input force is a driving temperature and the output reaction is heat loss. Appropriate modeling of the space environment is added to capture its effect on the radiator. The design parameters chosen for this radiator shape optimization problem fall into two classes, variable height along the width of the radiator and a spline curve defining the material boundary of the radiator. The implementation of multiple design parameter schemes allows the user to have more confidence in the radiator optimization tool upon demonstration of convergence between the two design parameter schemes. This tool easily allows the user to manipulate the driving temperature regions thus permitting detailed design of in‐space radiators for unique situations. Preliminary results indicate an optimized shape following that of the temperature distribution regions in the “cooler” portions of the radiator. The results closely follow the expected radiator shape.

Leakage power is a paramount concern in the design of Field Programmable Gate Arrays (FPGAs), and process variations have aggravated the problem. At the 45 nm technology node and beyond leakage variations can diminish the power yield of a design. To handle the increased complexity of the state-of-the-art designs, FPGAs have been scaled in size and complexity, leading to increased leakage, and more variation in leakage power. In this paper impact of process variations on the leakage in FPGAs is analyzed and variability aware CAD algorithms for mitigating the impact of process variations are developed. A programmable dual-Vdd FPGA architecture is selected on which these algorithms are implemented to evaluate the improvement in the power yield of FPGAs. The results indicate that the proposed CAD technique leads to 3%-9% improvement in the power yield.

The complexity of integrated circuits requires a hierarchical design methodology that allows the user to divide the problem into pieces, design each piece independently, and assemble the pieces into the complete system. The design hierarchy brings out composition problems, problems that are a property of the assembly as a whole, not of one single instance in the hierarchy. Recent research has produced tools that automate part of the composition task--the logical connection of the pieces. However, these tools do not ensure that signals driven over these connections will be driven sufficiently to give reasonable cycle speed of the resulting chips. It is easily possible to specify an assembly in which a small-sized gate is required to drive an enormous load. Parasitic capacitance of the wiring made automatically by the logical connection tool can be the dominant source of delay, so assembly tools can actually worsen the performance of the circuit and hide this fact from the designer. When required to make large circuits, automated layout tools such as PLA generators can blindly make layouts that give abysmally poor performance. Here again, the delay is in a part of circuit that the designer did not specify, so it is hidden. Finding and correcting these problems is a difficult and time-consuming task in integrated circuit design, and one that consumes vastly more people's time and computer time than the simple assembly of the chip. The task of guaranteeing that circuits meet performance specifications has been left mainly to the designer. Computer aided design has provided analysis tools, tools that tell the designer the performance statistics of the current design. It is then the designer's burden to interpret the performance statistics and use them as guides to make changes in the circuit. This thesis views performance optimization as an electrical composition task. Poor performance as a result of mismatched loads on devices in a problem of composition and should be corrected by the composition tool. Such a tool is presented in this thesis--a program that automatically sizes transistors in a symbolic description of a chip to match the load the transistors are driving. The results are encouraging: they show that delays can be cut by a factor of two in many current designs.

Numerical simulation method of thermal analysis for bridges without using field measurements