Thirteen-Level Multilevel Inverter Structure Having Single DC Source and Reduced Device Count

The performance analysis of modified multilevel DC link inverter (MMLDCLI) operating with various carrier‐based pulse width modulation (CB‐PWM) techniques is studied. In MMLDCLI, seven‐level is achieved with six controllable switches only, making it an attractive option as a reduced device count multilevel (MLI, multilevel inverter) topology. MMLDCLI operates with two different levels of voltage source, and the absence of transformer makes this topology suitable for photovoltaic (PV) applications. Two different levels of sources can be achieved with two different combinations of PV panel arrangements. The CB‐PWM is reputed modulation approach for MLIs. In this study, various CB‐PWM techniques are implemented for MMLDCLI to evaluate performance parameters such as harmonic analysis, device losses and device stress. All the simulations are performed in SIMULINK, and hardware prototype is developed to validate the results.

Multilevel inverters have gained significant attention in recent years due to their ability to achieve higher voltage and lower harmonic distortion compared to conventional two-level inverters. Pulse width modulation (PWM) techniques play a crucial role in controlling multilevel inverters by generating the required switching signals for their power electronic devices. This paper presents a comprehensive comparative analysis of various PWM techniques employed in multilevel inverters, including sinusoidal pulse width modulation (SPWM), space vector pulse width modulation (SVPWM), carrier-based pulse width modulation (CBPWM), and selective harmonic elimination (SHEPWM). Each PWM technique's advantages, limitations, and suitability for different multilevel inverter topologies are discussed. Furthermore, recent advancements and hybrid PWM techniques are also examined to explore potential improvements in performance and efficiency. This paper aims to provide researchers, engineers, and practitioners with valuable insights into selecting the most appropriate PWM technique for their specific multilevel inverter applications, considering factors such as performance requirements, cost constraints, and ease of implementation.

In this paper, a feedforward proportional carrier-based pulsewidth modulation (PWM) is proposed for the dc link control of the single-phase cascaded H-bridge multilevel photovoltaic inverter. The conventional carrier-based PWM techniques, such as the phase-shifted PWM and the level-shifted PWM, require multiple individual dc voltage controllers for the individual maximum power point tracking (MPPT). Thus, the control structure and the controllers' designs are quite complex. Several noncarrier-based PWM techniques, such as the feedforward space vector modulation, the sorting-algorithm-based modulation, and the lookup table-based modulation, have the capability of individual dc voltage regulation. Although these noncarrier-based PWM techniques require only one total dc voltage controller in the outer voltage loop, the implementations of them are much more complicated than those of the carrier-based PWM techniques. In this paper, with the proposed feedforward proportional carrier-based PWM, each individual modulation signal is directly generated by multiplying the current loop controller's output and the modulation signal's feedforward proportional factor. With the feedforward PWM and the total dc voltage control, the individual dc voltage regulation is achieved. This carrier-based PWM combines the strengths of both the traditional carrier-based PWM and the noncarrier-based PWM. It is not only easy for implementation, but also requires only one total dc voltage controller in the outer voltage loop. The detailed description, derivation, and analysis of this modulation are included in this paper. In addition, the simulations and experiments demonstrate the performance of the dc link control and the individual MPPT using the proposed PWM and the control strategy.

Neutral point clamped (NPC) inverter faces the problem of fluctuating neutral-point potential (NPP), which leads to severe problems like increase in total harmonics distortion (THD) of output voltage and increase in voltage stress of the power semiconductor switches. This paper is focused on hybrid techniques used for reducing fluctuations in NPP by means of balancing the voltage across dc-link capacitors. A technique of providing offset in carrier waves using phase disposition pulse width modulation (PDPWM) is proposed to ensure the voltage balancing. The drawback of this scheme is it does not work satisfactorily for four-level and five-level mode of operations of the inverter. It works as intended up to three-level operation. Other approach to achieve the task is based on carrier less PWM technique. In this technique, the redundancy of switching states in voltage state phasor diagram is used. The limitation of this technique is that it provides dc-link balancing up to modulation index 0.5 due to its inherent characteristics. To provide dc-link voltage balancing above 0.5 modulation index, external hardware is required. Using hybrid combination of bidirectional buck-boost chopper and SVPWM scheme, the dc-link voltage balancing for the entire range of operation of inverter is obtained. MATLAB simulation of this technique is carried out on three-phase, 50 Hz, 4 pole, 400 V squirrel cage induction motor. For experimental verification of the proposed technique, three-phase five-level NPC inverter is used with three-phase star connected 100 Ω resistors.

Single stage boost multilevel neutral point clamped (NPC) Z-Source inverter are becoming prominent for better power quality in low power and medium power applications. The conventional multilevel NPC Z-Source inverter uses two equal DC sources or a split DC source as well as two inductors, two capacitors and two diodes in the intermediate network. However, the source current is discontinuous in NPC Z-Source inverter (ZSI) which is not desirable in some of the applications like fuels cell, UPS system, hybrid electric vehicle etc. Though source current is continuous in multilevel quasi Z-source inverter (q-ZSI), but it uses more number of high power passive reactive elements (inductors and capacitors) which increases the system size, weight and cost. In this paper a three level voltage boost NPC inverter is proposed, which can boost the input DC voltage and give required three level AC output in a single stage. It uses less number of high power passive elements (one inductor and two capacitors), four diodes and two active switches in the intermediate network at the same time retains all the advantages of conventional three level NPC ZSI/q-ZSI. As a result, system size, weight and cost are reduced. Along with the above advantages, proposed inverter requires a single DC source and the source current is continuous in nature. The steady state mode of operation of the proposed inverter is discussed and voltage gain function is derived. The PWM technique for the inverter is also discussed. The simulation and experimental verification of the inverter has been done using MATLAB Simulink and laboratory prototype respectively.

This thesis presents design and implementation of a 20 kVA division-summation (D-Σ) digital controlled three-phase four-wire multi-function inverter system. The in-verter can be operated in grid-connected or stand-alone mode to act as a renewa-ble-energy ac power-supply system. In the stand-alone mode, the control of this in-verter uses the D-Σ digital control law for voltage tracking which includes load im-pedance estimation and repetitive control, causing the inverter can stabilize sinusoidal output voltage for unbalanced load and nonlinear load. For the grid-connected mode, in order to achieve a specific PF and stabilize grid voltage and frequency, the control is the D-Σ digital control law for current tracking which supplemented by a droop control based linear P-Q compensation. Moreover, the D-Σ digital control law in this research is based on Two-Phase Modulation (TPM) scheme and associated with the switching sequence transformed from space vector pulse width modulation (SVPWM) scheme, and thus, the inductance variation can be taken into account, reducing core size significantly. Finally, the control laws are verified with measured results from a 20 kVA three-phase four-wire inverter system.

In this article, a multilevel inverter (MLI) scheme is proposed for four-pole (4-pole), nine-phase (9-phase) induction motor (IM) drives with improved dc bus utilization as well as reduced device count. The proposed MLI is realized with nine three-switch inverter legs (3-SIL) and a single dc source. In the proposed MLI, each 3-SIL is utilized for exciting the two identical voltage profile coils/phase of the four-pole (4-pole) stator winding, which means each leg has to be modulated with two references. These two independent references/leg will limit the modulation index (M.I) of 3-SIL-based proposed MLI. This lower M.I will result in a requirement of the higher magnitude of dc-link voltage to achieve the rated load voltage requirement. In this article, an effective phase reconfiguring concept is proposed for reducing the dc-link voltage requirement of the proposed MLI. In addition, all the possibilities of phase reconfiguring details for proposed MLI-fed 9-phase IM drive are also presented. A three-phase carrier-based space vector pulsewidth modulation is implemented for improving the linear modulation range of proposed MLI configuration further. In contrast with existing 9-phase three-level inverters, like NPC and FC, the proposed MLI configuration requires only one dc link (with half of the magnitude) and lesser number of semiconductor devices. The proposed MLI-fed, 5 hp, 9-phase, 4-pole IM drive is validated by using Ansys Maxwell FEM simulation and experimental prototype for entire modulation range.

Multilevel converters are very popular in medium/high power conversions due to their capability to generate high quality voltage magnitudes with low harmonics while employing devices of smaller voltage ratings. The output voltage waveform of multilevel inverter consists of multiple steppes of smaller magnitudes designed to reduce electromagnetic interference (EMI) commonly produced by rapid switching that generate lesser common mode currents at motor shaft and bearings due to reduced dv dt . The neutral point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) converters are considered as the three classical multilevel converter topologies which have found their way to industrial applications almost two decades ago. To expand the application field of multilevel converters by overcoming the challenges associated with classical topologies, new multilevel topologies and modulation techniques are developed. In this thesis, various NPC multilevel inverter topologies and its modulation techniques are investigated. Diode-clamped multilevel inverter (DCMI) for more than three-level operation is less attractive due to dc-link capacitor voltage unbalancing issues and increased conduction loses caused by the commutation of (n-1) × (n-2) clamping diodes connected in series per-leg of an n-level diode clamped inverter. A converter topology with minimum number of series connected devices which balance the total voltage equally between the semiconductors and new multilevel modulation schemes, which on more number of levels, redundant voltage vectors and zero common mode voltage vectors available in higher level DCMI, can be used together to solve the above mentioned issues. In this thesis, the voltage unbalance issues and capacitor voltage balancing techniques in DCMI are studied in detail. An extensive analysis of two modulation techniques, level-shifted PWM (LS-PWM) and space vector modulation (SVM) are presented and a SVM based voltage balancing strategy for three-level and five-level diode clamped inverters are developed by utilizing redundant switching vectors without the need of any additional controls or auxiliary circuits. The proposed balancing strategy is tested on a five-level reduced device topology. Multiple-pole multilevel diode clamped inverter (M2DCI) which is derived from three-level DCMI topology and uses lesser number of clamping diodes compared to the classic five-level DCMI. The capacitor currents as well as dc-link intermediate branch currents are obtained from the switching function model of five-level M2DCI, which reduces the number of calculations at each sampling periods while implementing the voltage balancing strategy when compared to sector based methods. The stability limits of the proposed voltage balancing strategy for M2DCI based on load power factor angle and modulation indices have been obtained at various load conditions. The investigations shown here are modeled in Matlab/Simulink® and PSIM environment and verified using experimental results. It is found that to achieve capacitor voltage balancing, modulation index is restricted to about 60% of its maximum value when loads of high power factor i.e PF ≥ 0.8 is connected at the converter terminals. Hence the proposed reduced device topology with SVM technique, which self-balances the dc-link capacitors has been extended for reactive power control in a grid connected environment. Additionally, the application of five-level multiple-pole multilevel diode-clamped converter (M2DCC) as STATic synchronous COMpensator (STATCOM) is investigated with the proposed space vector modulation based balancing strategy. The proposed scheme maintains a balanced voltage across the dc-link capacitors and exchange reactive power at various load conditions. Further, the performance of STATCOM and controllers are investigated through modelling done in Matlab/Simulink® and PSIM environment. The proposed reduced device topology together with SVM based voltage balancing technique is expected to give good performance for reactive power applications by reducing the converter losses, size, weight and THD.

This paper introduces a new voltage balancing circuit for Neutral-Point-Clamped (NPC) Multilevel Inverter (MLI). The proposed circuit consists of switched-capacitors network which can easily balance the NPC-MLI by using proper switching state in carrier-based Pulse Width Modulation (CB-PWM) technique. This new voltage balancing network is readily extendable for using at higher-levels (e.g. 4, 5, 6 …)that facilitate the balancing problem in NPC-MLIs. Moreover, one of the most important features of the proposed balancing network is that it uses only one DC source at the input and can increase the input dc voltage to a higher level at the output without using any magnetic elements. This let the converter operate with the capability of boosting the input at the required output voltage with the ability of self-balancing. The simulation by using MATLAB/Simpower System and experiment set up of the proposed system has been conducted for three-phase four-level NPC-MLI which confirm the ability of the proposed circuit to balance the capacitor voltages properly.

This article presented a cost-effective 17-level voltage-boosting switched-capacitor (SC) inverter. To generate a 17-level staircase waveform, the suggested design uses twenty switches, four capacitors, and a single DC source. The series and parallel technique immediately resolves the capacitor voltage balance issue. The structure description, operating principle, computation of the optimal capacitance values, and modulation mechanism are all explained in brief. In terms of component per level factor, voltage gain, total standing voltage (TSV), blocking voltage, cost function, comparisons with the existing switched capacitor multilevel inverter (MLI) demonstrate the proposed topology strengths.

The current work proposes a novel design of Cascaded H-bridge (CHB) and half-bridge for an asymmetric hybrid Multi-Level Inverter (MLI) to generate a nine-level output using a reduced number of power switches. By utilizing three unequal DC voltage sources, the proposed topology achieves an extended range of nine-level output voltages while maintaining a simplified and compact architecture. A comprehensive evaluation of the proposed asymmetric MLI was conducted, namely, the cost function, component count per level, and total standing voltage. The output performance of the proposed MLI was evaluated using three carrier-based Pulse Width Modulation (PWM) techniques: Phase Disposition (PD), Phase Opposition Disposition (POD), and Alternate Phase Opposition Disposition (APOD), and by simulating in MATLAB Simulink a Photovoltaic (PV) system under variable irradiance. The simulation results revealed that the PD technique demonstrated superior performance in achieving the lowest Total Harmonic Distortion (THD) of 13.98% at a modulation index of 0.95. A comparative analysis was performed with other existing topologies. The proposed topology achieved a Total Standing Voltage per unit (TSVPU) of 18 VDC and cost function values of 4.75 and 6.25, while the total component count per level was calculated as 1.67, which is comparatively lower than that of the existing topologies. In conclusion, the reduction of the switch count significantly decreases the switching losses, system complexity, and installation costs compared to traditional MLI configurations.

The photovoltaic (PV) power conditioning system for small-scale applications has gained significant interest in the past few decades. However, the standalone mode of operation has been rarely approached. This paper presents a two-stage multi-level micro-inverter topology that considers the different operation modes. A multi-output flyback converter provides both the DC-Link voltage balancing for the multi-level inverter side and maximum power point tracking control in grid connection mode in the PV stage. A modified H-bridge multi-level inverter topology is included for the AC output stage. The multi-level inverter lowers the total harmonic distortion and overall ratings of the power semiconductor switches. The proposed micro-inverter topology can help to decrease the size and cost of the PV system. Transient analysis and controller design of this micro-inverter have been proposed for stand-alone and grid-connected modes. Finally, the system performance was verified using a 120 W hardware prototype.

In Cascaded Multi-Level Inverter (CMLI), the multi DC source and single DC source of asymmetrical and symmetrical Multi-level Inverters (MLI) are analyzed in this research paper. In single DC source, the switching pulse generation for nine-level H-bridge CMLI is generated using Phase Disposition Pulse Width Modulation (PDPWM). Here, four H-bridge CMLI has parallel connection, and the output of each H-bridge CMLI with the primary side of the transformer is also linked in parallel. The secondary side of the transformer is connected in series with load. It consists of one H-bridge inverter, 8 diodes, and two-bidirectional switches for bidirectional current flows through two switch S5, S6, and S7. The capacitor C4, C3, C2, and C1 are meant to separate the input DC voltage by Vdc, 3Vdc/4, Vdc/2, and Vdc/4. In multi DC source of symmetrical and asymmetrical CMLI switches are controlled by using Low-Frequency Pulse Width Modulation Technique (LFPWM). The nine-level symmetrical CMLI DC voltage source are Vdc1 = 1, Vdc2 = 1, Vdc3 = 1, and Vdc4 = 1. The 31-level asymmetrical CMLI DC voltage source are Vdc1 = 1, Vdc2 = 2, Vdc3 = 4, and Vdc4 = 8. All the multi DC Source and single-DC source of CMLI are analyzed in MATLAB software platforms. Comparison of the results with these simulations has been made, and the performance of the proposed system indicated by the THD. Hardware implementations have been done for asymmetrical MLI by using TMS320F2802A processor.KeywordsAsymmetrical and symmetrical multi-level inverterTMS320F2802A

In hybrid microgrids, integration of the low voltage renewable energy sources to high voltage AC and DC buses of grid requires a multiple voltage conversions. These conversions include low voltage to medium voltage and medium voltage to high voltage. When the number of conversions are increased the device count increases and power quality decreases. With this intent, this paper proposes a DC-AC/DC Three Port High Step-up Multi-level Converter (TPHSMC) topology. It has one input and two output ports namely low voltage DC input port, high voltage AC and high voltage DC output ports. The converter is a combination of switched capacitor with single DC source arrangement ( for producing multilevel boost output DC levels using single input DC source), auxiliary switches and H-bridge inverter. Operation of the converter topology is explained with the help of a single DC source nine-level high step-up three port converter. An appropriate control scheme is described and simulation results are presented using MATLB/Simulink. The proposed TPHSMC topology compared with existing topologies in aspects of power quality, device count, size of passive elements, boosting and three-port capabilities are presented to illustrate the effectiveness of the proposed converter.

Multilevel inverters have been forecasted in recent years for industrial and renewable energy applications due to its inherent characteristics of shaping the output voltage nearer to sinusoidal shape through concatenating several two/three level inverters using isolated DC sources or DC-link capacitors. However, the classical topologies used for synthesizing stepped voltage have several outwards like more number of DC sources or DC-link capacitors and switching devices used. In this paper, an effort has been sighted to bring a new topology for generating stepped voltage to overcome the above mentioned demerits. In addition to this, a new digital pulse width modulation (PWM) strategy is developed in-line with a new topology to eliminate the use of carrier and reference signals. The performance of the proposed topology and developed control strategy are evaluated in MATLAB/ Simulink platform and an laboratory prototype is constructed for experimental investigations to accord the simulation results.