Through Silicon Via interposer for millimetre wave applications

Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal integrity issues in TSVs is one of the major challenges of 3D integration. In this paper, different materials for the cores of the vias and the interposers are investigated to find the best possible combination that can reduce crosstalk and other losses like return loss and insertion loss in the TSVs. We have explored glass and silicon as interposer materials. The simulation results indicate that glass is the best option as interposer material although silicon interposer has some distinct advantages. For via cores three materials — copper (Cu), tungsten (W) and Cu-W bimetal are considered. From the analysis it can concluded that W would be better for high frequency applications due to lower transmission coefficient. Cu offers higher conductivity, but it has larger thermal expansion coefficient mismatch with silicon. The performance of Cu-W bimetal via would be in between Cu and W. However, W has a thermal expansion coefficient close to silicon. Therefore, bimetal Cu-W based TSV with W as the outer layer would be a suitable option for high frequency 3D IC. Here, we performed the analysis in terms of return loss, transmission coefficient and crosstalk in the vias.

In this paper, we show the advantages of 3-D stacked through silicon via (TSV) in high chip density package in aspect of wideband and low power distribution network (PDN) impedance. We selected large size (80 μm) and large pitch (200 μm) TSV with thick silicon substrate (Si, 80 μm, aspect ratio =1) for on-chip PDN, and compared two total PDN impedances of a PDN with TSVs and a PDN with wire-bondings depending on number of stacked chips from 2 to 10 on a single package. PDN impedance with TSVs includes total capacitance and inductance of TSV and 20 mm × 20 mm package substrate. PDN impedance with wire-bondings shows total capacitance and inductance of wire-bondings and same size package substrate. PDN impedance with TSVs has lower levels with wide bandwidth from 10 MHz to 5 GHz except serial resonance frequency range of the package substrate around 350 MHz. In low frequency range from 10 MHz to 350 MHz, total capacitance of a PDN with TSVs is larger than that of a PDN with wire-bonding because of 0.1 μm thickness silicon oxide (Si02) for blocking DC leakage from TSV to Si substrate. Over 350 MHz, total inductance of a PDN with TSVs is smaller than that of a PDN with wire-bonding because TSV is the smallest electrical path from top surface of stacked chips to the package PDN. The effectiveness of lowering total PDN impedance is better when the number of stacked chips is growing because total length of TSVs is linearly increased with factor 1 while total length of wire-bonding is done with factor √2.

A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a compelling alternative to 3-D IC stacking of logic and memory devices with TSVs. The 3-D IC stacking approach to achieve high bandwidth has several drawbacks, including the need for TSVs through the logic die, thermal management within the 3-D stack, and the high manufacturing cost associated with wafer-based TSV processing. This paper presents design, fabrication, and electrical characterization of small TPVs (15–40 $\mu{\rm m}$ in diameter) in 30- $\mu{\rm m}$ thin glass to achieve an ultrathin 3-D interposer. This paper also reports the first demonstration of ultrasmall TPVs in glass (15 $\mu{\rm m}$ ) with same dimensions as TSVs in silicon. The signal insertion loss and crosstalk behavior of TPVs in ultrathin glass were investigated and found to be superior to TSVs using 3-D electromagnetic simulations. In demonstrating the 3-D interposers, two process-related challenges were addressed in this paper, namely: 1) defect-free formation of ultrasmall TPV holes with diameters of 15 $\mu{\rm m}$ at 27- $\mu{\rm m}$ pitch and 2) TPV metallization with copper. The fabricated TPVs in ultrathin glass showed a good model to hardware correlation of signal transmission with insertion loss ${ at 20 GHz. The results in this paper suggest that the 3-D interposer concept can be a simpler alternative to 3-D IC stacking with TSVs to achieve high bandwidth between the logic and memory devices.

An air-isolated through-silicon via (TSV) technique is proposed to reduce radio-frequency (RF) losses in silicon interposers. A testbed containing air-isolated and conventional TSVs is fabricated and characterized from 10 MHz to 20 GHz with an L-2L de-embedding technique. The proposed air-isolated TSV technique yields 46.7% lower insertion loss compared to conventional TSVs at 20 GHz from 3-D full-wave simulations and measurements. Moreover, the impact of the air-isolation region width between TSVs on capacitance and conductance is quantified.

Based on the extracted equivalent parasitic parameters, the distributed transmission line model of a mixed carbon nanotube bundle (MCB) built signal-ground-signal-type differential through silicon via (TSV) is established and validated against the multiconductor transmission line model (MTL) results and predictive experiment results over a wide frequency range. Using the proposed model, the effect of various dimensional parameters and material properties on the signal loss and characteristic impedances of the differential TSV interconnect is investigated for odd- and even-mode signal propagation, respectively. It is observed that dielectric thickness is the most important factor affecting the transmission characteristics of TSV interconnects for the proposed TSV configuration. Moreover, various electrical performances of the proposed differential TSV, such as insertion loss, eye opening area, characteristic impedances, and 50% time delay are evaluated and compared to that of a signal-ground-type single ended TSV interconnect. The results presented in this paper will be helpful to fully understand the CNT-TSV electrical characterization and provide some signal integrity-aware guidelines for circuit designers in early planning stage.

TSV (Through-Silicon Via) 3D packaging technology has been and continues to be investigated by many of the semiconductor manufacturer and research institute as a practical way to achieve higher performance and smaller form factors. Compared with conventional 2D packaging, this can increase packing density and reduce power consumption dramatically because of shorter interconnection by vertical directional stacking. So far 3D stacking technology based on W2W bonding has developed widely such as 3D Image sensor and 3D stacking memory because it has the advantage of easier alignment and higher throughput compared with chip-to-chip bonding. However, the wafer level 3D stacking method can be only applicable to products with high production yield because overall yield of 3D stacking chips depends on the yield of multiple stacked layers. In this paper, we suggested wafer level build-up stacking process using oxide bonding and molten metal filling newly, which temporary bonding process is unnecessary and demonstrated it through experiments. Thermal stress analysis was carried out to compare the structural reliability between conventional TSV and the proposed TSV model. The simulation results indicate that the proposed TSV model is more reliable than the conventional model with respect to stress in the stack chip.

Two vertical transitions with through silicon vias (TSVs) in 3D die stack are designed and their high frequency electrical characteristics are presented in this paper. The two vertical transitions consist of TSVs for obtaining electrical connection between the die front side and back side. Back side redistribution layer is eliminated in the designs to simplify the fabrication process without sacrificing the electrical performance. Design considerations and guidelines are provided to design high speed TSV structure up to 50 GHz. Different kinds of transmission line interconnects (for instance, microstrip line and coplanar waveguide) are implemented at the input/output extensions for different applications. For both vertical transition designs, the simulated insertion loss is better than 0.65 dB up to 50 GHz while good impedance matching from DC to 50 GHz is obtained with the simulated return loss greater than 14 dB.

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via (TSV) with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab. for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance (RLGC) model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6&. on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6∼4.0 times higher bandwidth than the conventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.

This paper presents a study of the propagation parameters (impedance and propagation constant) for interconnection structures implementing interconnection lines (wafer front and backside) combined with Through Silicon Via (TSV). Lifetime acceleration experiments are conducted on these structures and indicate a significant variation of the propagation parameters across lifespan. The underlying physical mechanism is demonstrated and an activation model for the prediction of the line parameter variation is proposed. TSV-last processes have been considered by industry for the implementation of 3D interconnects into various kind of silicon substrates already functionalized on the front side. This is possible thanks to a TSV process with a low temperature budget (<200°C), guaranteeing the compatibility with most of the pre-existing MOS and passive technologies. IPDiA is offering this type of TSV technology in combination with the PICS passive platform (Passive Integrated Connecting Substrate). Several test vehicles have been implemented and excellent performances have been observed in the small signal/RF domains; electrical models have been extracted from test silicon and are showing a good agreement with simulation results and earlier literature. Application domains with permanent bias have also been considered and non-linear effects related to the semiconductor nature of the substrate have been reported (i.e. drift-diffusion). However, the effect of electrical and thermal stress that might arise from severe applications or long lifespan, and their impacts on TSV electrical stability, have not yet been reported in the literature. This works concentrates on the study of the instability modes that are related to the TSV dielectric aging under permanent bias accelerated by temperature. To avoid effects from other mechanisms (like, for example, copper diffusion in the oxide) under the selected acceleration conditions (Efield<10MV/cm, temperature <100°C), specific test structures (planar CPW) are designed. It consists of an AlSi (0.5%) metallization, which is isolated from the P type HR (High Resistivity) substrate by TSV isolation dielectric. Four different flavors of dielectric are proposed: PECVD oxide deposited at 150°C/200°C combined/not with a thermal oxide liner. When implemented, the liner is intended to enhance the dielectric/silicon interface, thus allowing to differentiate the effects of fixed charges, mobile charges, and interface states density. A strong correlation is found between charge density within the dielectric and the CPW loss and characteristic impedance. While line loss increases with charge density, the opposite behavior is observed for the characteristic impedance. Furthermore, under CVS (constant voltage stress) at 7.5 MV/cm under 100°C, a displacement of mobile charges into the dielectric is observed, that correlates to the variation of the CPW performances. FTIR analysis indicates that the mobile charges are related to the presence of silanol/hydroxide ions resulting from moisture absorption in the oxide. Similar effects are observed on real 3D TSV structures. An activation model is derived from previous results, which allows predicting the evolution of the CPW characteristics as a function of thermos-electrical stress.

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Fundamental limitations of ionized Physical Vapor Deposition (iPVD) copper seed, and Chemical Vapor / Atomic Layer Deposition (CVD/ALD) barrier coverage in deep Through Silicon Vias (TSV), coupled with unavoidable high capital investments, are holding back the industry-wide adoption of Three-Dimensional Integrated Circuit (3D-IC) solutions. Electrografting (eG) [1] generates surface-initiated conformal films on (semi)-conducting materials – such films are adherent, uniform, thin and continuous. eG is a wet-process technique, operated in standard plating tools, which has proven its efficiency to deposit copper seed layers for interconnect Back End Of Line (BEOL) [2] and TSV [3,4] applications. Chemical grafting (cG) is a similar technology, used to graft films on non-conductive surfaces. Wet deposition of insulator, barrier and copper seed layers has been performed inside deep TSVs, using a combination of eG and cG. TSVs formed using these layers meet key unit process requirements such as conformality, uniformity, good electrical and mechanical properties, low contamination level and adhesion [5]. The present paper describes the integration of such layers in conventional TSVs metallization process flows (up to 300-mm Si wafers), focusing on Cu filling compatibility in various TSVs dimensions. Conventional Electro Plating Deposition (ECD) performed after copper seed to complete via metallization shows weak properties associated to: strong acidic attack of the copper seed, high amounts of contaminants (Cl, S and C) and low uniformity when deposited on top of resistive seed layers. A new mildly basic TSV plating chemistry is presented here, to be deposited on top of various thin layers including electrografted films, with low attack of the seed layer, low contaminants and high uniformity on resistive seed layers.

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

Requirements of a quantum beam imager such as a vertex detector in high energy physics experiment are intelligent functions which are realized by embedding memories of quantum beam hit-position, hit-charge, and hit-timing in a pixel with keeping small pixel size to achieve high spatial resolution. To satisfy the requirements, circuit layer stacking on a sensor, i.e., three dimensional (3D) technology, has been widely studied and proposed. The Silicon-on-Insulator (SOI) sensor is one of the 3D sensors because the circuits in the top silicon layer is on the sensors of the bottom silicon substrate. The circuits and sensors are electrically connected by submicron W filled vias through the buried oxide (BOX), which are called as through BOX vias (TBV). Thus, the SOI sensor has extremely higher fill factor than the bulk-CMOS sensor. In order to achieve more intelligent functions in the pixel, however, the pixel size by using the simple SOI technology is large to get the required spatial resolution. Therefore, multiple circuit layer formation by chip stacking technology is adopted. In this chip stacking, a fine pitch micro-bump technology with two-tile face-to-face stacking is employed because of the simplest 3D structure. The target of micro bump diameter and spacing are 2.5 μm and 5 μm, respectively. The SOI 3D chip stacking process is starting with the base chips which are fabricated by an 8 inch 0.2 μm fully depleted SOI pixel sensor process with five metal layers. After the metal 5 etching, an oxide film is deposited and planarized by chemical mechanical polishing (CMP). W-filled vias to a under bump metal is formed at bump formation areas. After the under bump metal deposition and patterning, metal bumps are formed. Then, two chips which are lower and upper chips are aligned and bonded face-to-face at 200℃ followed by adhesive injection. To make bonding pads on the upper chip, the upper chip handle silicon is etched until exposing the BOX and TBV by wet solution. TBV can easily connect between circuits in the upper chip and the bonding pad metal without any through silicon via (TSV) process. This is the most superior point to use the FD-SOI pixel sensor in 3D structure. The TBV size is around 0.3 μm which is much smaller than a conventional TSV whose size is around 5 μm by using the most advanced technology. In addition, this TBV can be used as interconnections between multiple chips without any TSV. Finally, bonding pad and passivation formation are done. For micro bump formation, a gold bump was utilized because the gold is oxidation-resistant metal. The micro gold bump was fabricated by two methods. One is a cone shaped gold bump manufactured by a gold nanoparticle deposition with a photoresist lift-off technique [1]. The cone shaped gold bump with 2.5 μm in diameter and 2.5 μm in height are successfully formed on the under bump metal layer. Because of the nanoparticle deposition, the gold bump is easier to deform by the bonding. Thus, the collapsibility allows low stress to the die and high reliable junctions. It is also confirmed that the bump resistance is approximately 0.25 Ω/bump from daisy chain measurement. The other is a gold cylindrical bump using a combination of inverse-tapered photoresist and low incident angle sputtering [2]. Because of narrowing at the top, lower pressure to collapse between the bumps is required than the gold cone bumps. This may also improve bump yield and reliability. 0.37 Ω/bump of the bump resistance is obtained by the gold cylindrical bumps. Using the FD-SOI 3D chip stacking technology with the cylindrical bump, the pixel sensor designed for the International Linear Collider (ILC) vertex detector called SOFIST was fabricated and the chip photo is shown in the figure. In SOFIST, hit-position, hit-charge, and hit-time memories are embedded in each pixel by the 3D micro bump bonding with 20 mm pixel size. Owing to the removal of the handle silicon of the upper chip, the patterns of the lower chip can be seen through the upper chip oxide. The green patterns close to bonding pads are backsides of silicon layer in the upper chip. As shown in the figure, our 3D process technology is successfully introduced in FD-SOI quantum beam imager.

3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

The material effect on the thermal stress of annular-trench-isolated (ATI) through silicon via (TSV) was investigated. The ATI TSV with two sets of materials as the Cu core with the BCB insulator and solder core with parylene-HT insulator were successfully fabricated. A lower stress level was observed for the ATI TSV with a solder core and parylene-HT insulator in experiments and finite element method (FEM) simulation. In order to reveal the origin of the lower stress, the ATI TSVs with different core materials were simulated. The Si ring with high Young’s modulus and low CTE value blocked the effect of the different core material of ATI TSV inside the Si ring and maintained the stress in the Si substrate at the same level. The origin of the lower stress level in the Si substrate was determined to be the lower Young’s modulus and CTE of insulator Parylene-HT than BCB. Due to the surrounding structure of the Si ring, the effect of different core material on thermal stress in the Si substrate became weak. The discussion of the material effect on the thermal stress of ATI TSV provided further understanding of the structure with the Si ring.