Thursday Plenary: Anchoring Security in the Connected World

A system is as secure as its weakest link. Current computing systems employ a multiple-layer approach to build a trusted environment. At the bottom of this multi-layer approach is a hardware root of trust which other layers build upon. It is important to assure this root of trust is secure and free from any weakness. Recently there is surge of research topics on hardware security. In this talk we first narrow the topic a bit and outline a more restricted definition of hardware security. Upon this tighter definition we try to explain why it is so hard to defend hardware attacks. We will give example from the recent hardware attacks. We, then, focus on a few topics related to hardware security including hardware Trojans and IC counterfeiting. We argue why it is very unlikely for a reputable foundry such as TSMC to plant them. On IC counterfeiting, there have been work on employing Physically Unclonable Function (PUF) to prevent counterfeiting. In this talk we will attempt to explain the difference between testing of these hardware security elements from testing of standard logic elements. We will also clarify that foundry is in the best position to work with customers directly in building these elements such as Physical Unclonable Functions (PUFs) and Physical Random Bits Generators (PRBGs).

Counterfeiting of electronic goods and stealing of valuable and sensitive data has become a massive problem for companies, the economy and even the security of modern societies. In order to deal with these issues more and more security measures have to be put in place both at the system level as well as the device level. Since security solutions are only as strong as their weakest link, strong solutions can only build on strong foundations. It is widely accepted that secure hardware is a fundamental building block of a strong solution. In this talk we will introduce secure hardware technologies built on the intrinsic physical properties of the underlying device: Hardware Intrinsic Security. We will start by introducing the physical principles behind this concept. Next, we continue with the cryptographic primitives and the applications which can build upon these intrinsic hardware security foundations. These will be illustrated with some practical examples. Finally, we discuss existing challenges and new directions.

There exist many documents, guidelines and application-level programs attempting to secure various operating systems (OS), but there is much less documentation and software for protecting lower levels subsystems such as the Basic Input Output System (BIOS). Security professionals are well aware that the security on any system is as strong as its weakest link as an attacker will seek to break into a system with the least amount of effort. In this chapter we will focus on the BIOS, and describe its main functions as well as the potential for attacks and countermeasures. After discussing the BIOS and analysing how it might be compromised, we will go on to consider rootkits. Installing a rootkit is often the next stage of an attack once the BIOS has been compromised, allowing the attack to take full control of the target system. We will discuss what rootkits actually are, how to identify that a system has been infected with a rootkit, and how to try and prevent such attacks in the first place. It should be note that the issues raised in this chapter have also provided justification for specialist hardware security measures such as the Trusted Platform Module (TPM) [1, 2, 3] described in Chap. 4.

The U.S. Bioeconomy: Charting a Course for a Resilient and Competitive Future

The last half of the 20th century provided an opportunity for the explosive growth and development of research on writing. From a product-oriented to a process-oriented approach, new theoretical models of writing emerged. Following this shift in conceptual frameworks, new methods of investigations were applied in research. However, in the context of this development, careful analyses of the literature demonstrate clearly that systematic, theoretically-driven empirical research focused on writing has been barely measurable compared with research on speech production and language comprehension. Methods presented in this book illustrate how the study of writing processes is becoming ever more tractable with the use of real time methods that take advantage of their unobtrusive recordings of the writing process.

The explosive growth of AI-driven services has led to cloud-based Field Programmable Gate Array (FPGA) accelerators as key enablers of high-performance training and inference in modern data centers. Since 2024, the demand for deploying large AI workloads, especially Large Language Model (LLM), in the cloud has increased dramatically, intensifying competition among cloud providers and increasing pressure on shared FPGA infrastructures. This increasing reliance highlights the need for robust hardware security measures for cloud FPGAs. A particularly serious threat is fault injection attacks, which exploit dynamic voltage fluctuations to induce timing faults, potentially compromising functional integrity and bypassing cryptographic protections. However, existing verification procedures and structural Design Rule Check (DRC) remain blind to attacks embedded in benign-looking circuits. In this paper, we present Power-Wasting Neural Network (PWNN), a novel adversarial technique that leverages the inherent switching behavior of neural network operations to act as a power-waster circuit under adversarial input patterns. We systematically explore network architectures, and input patterns to craft configurations that induce voltage fluctuations capable of triggering timing faults for successful Differential Fault Analysis (DFA). Our PWNN implementation uses a standard open-source tool chain and passes all pre-implementation verification checks, while covertly inducing faults at runtime. We demonstrate on both the AMD ZCU104 and PYNQ-Z2 that PWNN can reliably cause timing faults on the critical path of a co-located AES-128 block cipher, enabling the rapid collection of correct/faulty ciphertext pairs needed for DFA-based key recovery. These results show that functionally correct, DRC compliant accelerators can serve as powerful, adaptive fault injectors that invalidate assumptions about bitstream security and hardware isolation.