Tile size selection of affine programs for GPGPUs using polyhedral cross-compilation

Loop tiling and unrolling are two important program transformations to exploit locality and expose instruction level parallelism, respectively. In this paper, we address the problem of how to select tile sizes and unroll factors simultaneously. We approach this problem in an architecturally adaptive manner by means of iterative compilation, where we generate many versions of a program and decide upon the best by actually executing them and measuring their execution time. We evaluate several iterative strategies. We compare the levels of optimization obtained by iterative compilation to several well-known static techniques and show that we outperform each of them on a range of benchmarks across a variety of architectures. Finally, we show how to quantitatively trade-off the number of profiles needed and the level of optimization that can be reached.

A thinned irregular tiled array synthesis approach is proposed for 5G base station array design. To fit the needs of multiusers, different sizes of vertical tiles with thinned elements ae considered. The tiling configuration and excitations are optimized to achieve high gain, low sidelobes, and wide-angle scanning simultaneously. A mixed integer second-order cone programming (MISOCP) model is obtained from convexity analysis and transformation. Besides, a generalized Benders decomposition algorithm is built to decouple the complex original problem into mixed integer linear programming (MILP) master problems and convex second-order cone programming (SOCP) subproblems, which is used to solve the large-scale problems efficiently. Irregular partition optimization is based on full-wave simulations of regular finite arrays. The joint effects of active VSWR and radiation patterns are considered to reduce the mismatch between element simulations and final performances. Numerical results show that the 5G array synthesized by the proposed approach is superior to those reported by the state-of-the-art methods in terms of both E- and H-plane scans and the number of T/R modules.

Loop tiling is an important compiler transformation used for enhancing data locality and exploiting coarse-grained parallelism. Tiled codes in which tile sizes are runtime parameters - called parametrically-tiled codes - are important for empirical tuning systems like ATLAS. Some recent work has addressed the problem of generating sequential parametric tiled code. In this paper we describe DynTile, a system for transforming untiled sequential input C code containing affine imperfectly nested loops to parametrically tiled code for parallel execution on multicore processors. The effectiveness of the system is demonstrated using a number of benchmarks on an eight-core system.

Integer programming and minimax problems are essential tools in solving various problems that arise in data mining and machine learning such as multi-class data classification and feature selection problems. In this paper, we propose a new hybrid harmony search algorithm by combining the harmony search algorithm with the multidirectional search method in order to solve the integer programming and minimax problems. The proposed algorithm is called multidirectional harmony search algorithm (MDHSA). MDHSA starts the search by applying the standard harmony search for numbers of iteration then the best-obtained solution is passing to the multidirectional search method as an intensification process in order to accelerate the search and overcome the slow convergence of the standard harmony search algorithm. The proposed algorithm is balancing between the global exploration of the harmony search algorithm and the deep exploitation of the multidirectional search method. MDHSA algorithm is tested on seven integer programming problems and 15 minimax problems and compared against 12 algorithms for solving integer programming problems and 11 algorithms for solving minimax problems. The experiments results show the efficiency of the proposed algorithm and its ability to solve integer programming and minimax problems in reasonable time.

Writing optimised compute unified device architecture (CUDA) program for graphic processing units (GPUs) is complex even for experts. We present a design methodology for a restructuring tool that converts C-loops into optimised CUDA kernels based on a three-step algorithm which are loop tiling, coalesced memory access and resource optimisation. A method for finding possible loop tiling solutions with coalesced memory access is developed and a simplified algorithm for restructuring C-loops into an efficient CUDA kernel is presented. In the evaluation, we implement matrix multiply (MM), matrix transpose (M-transpose), matrix scaling (M-scaling) and matrix vector multiply (MV) using the proposed algorithm. We present the analysis of the execution time and GPU throughput for the above applications, which favourably compare to other proposals. Evaluation is carried out while scaling the problem size and running under a variety of kernel configurations. The obtained speedup is about 28–35% for M-transpose compared to NVIDIA Software Development Kit, 33% speedup for MV compared to general purpose computation on graphics processing unit compiler, and more than 80% speedup for MM and M-scaling compared to CUDA-lite.

Non-volatile memory (NVM) is expected to be the second level memory (named remote memory) in two-level memory hierarchy in the future. However, NVM has the limited write endurance, thus it is vital to reduce the number of write operations on NVM. Meanwhile, in two-level memory hierarchy, prefetch is widely used for fetching certain data before it is actually required, to hide the remote memory access latency. In general, large-scale nested loop is the performance bottleneck in one program due to the write operations on NVM caused by the first level memory (named local memory) miss and data reuse. Loop tiling is the key technique for grouping iterations so as to reduce the communication with remote memory used in compiler. In this paper, we propose a new loop tiling approach for minimizing the write operations on NVMs and completely hiding the NVM access latency. Specifically, we introduce a series of theorems to help loop tiling. Then, a legal tile shape and an optimal tile size selection strategy is proposed according to data dependency and local memory capacity. Furthermore, we propose a pipeline scheduling policy to completely hide the remote memory latency. Extensive experiments show that the proposed techniques can reduce write operations on NVMs by 95.1% on average, and NVM latency can be completely hidden.

Optical Quadrature Microscopy (OQM) is a process which uses phase data to capture information about the sample being studied. OQM is part of an imaging framework developed by the Optical Science Laboratory at Northeastern University. In one particular application of interest, the framework is used to extract phase information from the image of an embryo to determine embryo viability.Phase Unwrapping is the process of reconstructing the real phase shift (propagation delay) of a sample from the measured wrapped representation which is between -π and +π. Unwrapping can be done using the Minimum LP Norm Phase Unwrap algorithm. Images are first preprocessed using an Affine Transform before they are unwrapped. Both of these steps are time consuming and would benefit greatly from parallelization and acceleration. Faster processing would lower many research barriers (in terms of throughput and performance) present when using OQM.In this paper we report on accelerating Phase Unwrapping and Affine Transformations using NVIDIA's CUDA programming model. We also run elementary noise removal on the GPU using NVIDIA's CUBLAS (CUDA Basic Linear Algebra Subprograms) library. We integrate GPU execution into a Matlab environment to seamlessly interface to the pre-existing image acquisition system. By mapping the unwrap and noise removal to a GPU, and by also reducing the amount of I/O overhead, we are able to accelerate the end-to-end process by more than 7.3x. This enables our imaging framework to perform high speed image acquisition and visualization at near real-time rates.

Modern Graphic Processing Units (GPUs) provide sufficiently flexible programming models that understanding their performance can provide insight in designing tomorrow's manycore processors, whether those are GPUs or otherwise. The combination of multiple, multithreaded, SIMD cores makes studying these GPUs useful in understanding tradeoffs among memory, data, and thread level parallelism. While modern GPUs offer orders of magnitude more raw computing power than contemporary CPUs, many important applications, even those with abundant data level parallelism, do not achieve peak performance. This paper characterizes several non-graphics applications written in NVIDIA's CUDA programming model by running them on a novel detailed microarchitecture performance simulator that runs NVIDIA's parallel thread execution (PTX) virtual instruction set. For this study, we selected twelve non-trivial CUDA applications demonstrating varying levels of performance improvement on GPU hardware (versus a CPU-only sequential version of the application). We study the performance of these applications on our GPU performance simulator with configurations comparable to contemporary high-end graphics cards. We characterize the performance impact of several microarchitecture design choices including choice of interconnect topology, use of caches, design of memory controller, parallel workload distribution mechanisms, and memory request coalescing hardware. Two observations we make are (1) that for the applications we study, performance is more sensitive to interconnect bisection bandwidth rather than latency, and (2) that, for some applications, running fewer threads concurrently than on-chip resources might otherwise allow can improve performance by reducing contention in the memory system.

DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make tiling legal and exploit wavefront parallelism across the tiles and within a tile. Thus, tile size selection, which is performance-critical, becomes more complex for DOACROSS loops than DOALL loops on GPUs. This paper presents a model-driven approach to automating this process. Validation using 1D, 2D and 3D SOR solvers shows that our framework can find the tile sizes for these representative DOACROSS loops to achieve performances close to the best observed for a range of problem sizes tested.KeywordsExecution TimeLoop NestThread BlockTile SizeActual Execution TimeThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this work we present an original GPU-only parallel matrix-matrix multiplication algorithm (C = αA * B + βC) for servers with multiple GPUs connected by NVLink. The algorithm is implemented using CUDA. The data transfer patterns, the communication and computation overlap, and the overall performance of the algorithm are considered. By regulating the commands call order and the sizes of tiles, we tune the uninterrupted asynchronous data transmission and kernel execution. Two cases are considered: when all the data are stored in one GPU and when the matrices are distributed among several GPUs. The execution efficiency of this new algorithm is compared with cuBLAS-XT from the Nvidia CUDA Toolkit library.

Deep learning has transformed the use of machine learning technologies for the analysis of large experimental datasets. In science, such datasets are typically generated by large-scale experimental facilities, and machine learning focuses on the identification of patterns, trends and anomalies to extract meaningful scientific insights from the data. In upcoming experimental facilities, such as the Extreme Photonics Application Centre (EPAC) in the UK or the international Square Kilometre Array (SKA), the rate of data generation and the scale of data volumes will increasingly require the use of more automated data analysis. However, at present, identifying the most appropriate machine learning algorithm for the analysis of any given scientific dataset is a challenge due to the potential applicability of many different machine learning frameworks, computer architectures and machine learning models. Historically, for modelling and simulation on high-performance computing systems, these issues have been addressed through benchmarking computer applications, algorithms and architectures. Extending such a benchmarking approach and identifying metrics for the application of machine learning methods to open, curated scientific datasets is a new challenge for both scientists and computer scientists. Here, we introduce the concept of machine learning benchmarks for science and review existing approaches. As an example, we describe the SciMLBench suite of scientific machine learning benchmarks. Finding the most appropriate machine learning algorithm for the analysis of any given scientific dataset is currently challenging, but new machine learning benchmarks for science are being developed to help.

With machine learning (ML) services now used in a number of mission-critical human-facing domains, ensuring the integrity and trustworthiness of ML models becomes all important. In this work, we consider the paradigm where cloud service providers collect big data from resource-constrained devices for building ML-based prediction models that are then sent back to be run locally on the intermittently connected resource-constrained devices. Our proposed solution comprises an intelligent polynomial-time heuristic that maximizes the level of trust of ML models by selecting and switching between a subset of the ML models from a superset of models in order to maximize the trustworthiness while respecting the given reconfiguration budget/rate and reducing the cloud communication overhead. We evaluate the performance of our proposed heuristic using two case studies. First, we consider Industrial IoT (IIoT) services, and as a proxy for this setting, we use the turbofan engine degradation simulation data set to predict the remaining useful life of an engine. Our results in this setting show that the trust level of the selected models is 0.49%–3.17% less compared to the results obtained using integer linear programming (ILP). Second, we consider smart cities services, and as a proxy of this setting, we use an experimental transportation data set to predict the number of cars. Our results show that the selected model’s trust level is 0.7%–2.53% less compared to the results obtained using ILP. We also show that our proposed heuristic achieves an optimal competitive ratio in a polynomial-time approximation scheme for the problem.

For low-power designs utilizing multiple threshold voltage (VT) levels such as using a mixture of regular, low, and super-low VT standard cells, a small perturbation on each VT level leads to a significant fluctuation of the leakage power consumption. In this context, this work addresses the problem of finding the value of each VT level on the target design with the objective of minimizing the total leakage power consumption of the design. Precisely, for a timing closed design, typically at the post-route stage, whose leakage power has already been optimized for a representative (i.e., nominal) value of each VT level, we explore the range of VT level values and fine-tune the VT values, so that the resulting leakage power of the design should be further minimized while not violating the timing constraints. To this end, we propose a near-optimal approximation technique based on a piecewise-linear programming formulation for the VT reassignment, incorporating the practical issue of circuit delay and leakage power recalculation incurred by VT tuning into linear programming constraints and objective. In the meantime, through experiments with benchmark circuits, it is shown that our VT tuning technique is five orders of magnitude faster than the conventional VT tuning while further reducing the leakage power by 5.41% under the circuit timing constraints.

It has been a long time that computer architecture and systems are optimized for efficient execution of machine learning (ML) models. Now, it is time to reconsider the relationship between ML and systems and let ML transform the way that computer architecture and systems are designed. This embraces a twofold meaning: improvement of designers’ productivity and completion of the virtuous cycle. In this article, we present a comprehensive review of the work that applies ML for computer architecture and system design. First, we perform a high-level taxonomy by considering the typical role that ML techniques take in architecture/system design, i.e., either for fast predictive modeling or as the design methodology. Then, we summarize the common problems in computer architecture/system design that can be solved by ML techniques and the typical ML techniques employed to resolve each of them. In addition to emphasis on computer architecture in a narrow sense, we adopt the concept that data centers can be recognized as warehouse-scale computers; sketchy discussions are provided in adjacent computer systems, such as code generation and compiler; we also give attention to how ML techniques can aid and transform design automation. We further provide a future vision of opportunities and potential directions and envision that applying ML for computer architecture and systems would thrive in the community.

This chapter presents a linear-programming-based optimal solution for an Optimal Placement Problem (OPP) of Synchrophasors or Phasor Measurement Units (PMU). With the increasing use of Synchrophasors for smart-grid monitoring and control, the problem with PMU placement has become a major concern due to its large installation costs. This chapter utilizes an Integer Linear Programming (ILP) approach to find optimal solutions. We show that the performance of our LP constraints and the formulation makes the ILP approach very attractive for smaller utilities that have limited budgets. This is shown using with and without zero-injection cases in programmed AMPL language using CPLEX solver. We also propose an Optimal Redundancy Criterion (ORC) which assists utilities with providing redundant observability for critical buses in the system. Our approach yields full and redundant observabilities within a few milliseconds for different cases, such as IEEE 300 test systems and an Indian power grid.