Time-referenced single-path multi-bit ΔΣ ADC using a VCO based quantizer

In the context of a /spl Sigma//spl Delta/ analog-to-digital converter (ADC) or digital-to-analog-converter (DAC), single-bit quantization is preferred because a 1b DAC is inherently linear. A multi-bit DAC needs to be linear to avoid being the performance-limiting factor in a CB converter. Aside from this drawback, multi-bit quantization is attractive because it improves /spl Sigma//spl Delta/ modulator performance by increasing the modulator resolution or increasing the modulator bandwidth, while at the same time whitening the quantization noise and improving modulator stability. Among many dynamic-matching schemes existing today, the butterfly shuffler is effective and practical. Thus far, schemes based on the butterfly shuffler are used to whiten or to 1/sup st/-order shape mismatch errors. This paper presents a model of the structure which shows how a butterfly shuffler can be endowed with arbitrary mismatch-shaping characteristics. A 2/sup nd/-order bandpass shuffler is given as an example. A 16-element switched-capacitor (SC) DAC is designed and fabricated with a 1.2 /spl mu/m double-poly CMOS process. An 8/sup th/-order bandpass /spl Sigma//spl Delta/ modulator is implemented on a Xilinx FPGA along with the 2/sup nd/-order bandpass shuffler to drive the DAC. The system diagram is shown. The harmonic distortion is reduced by as much as 27 dB, resulting in a dynamic range of 90 dB at 125 kHz center frequency.

The design of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators is presented. The 9 level DAC circuit uses a time-variant feedback pulse shape to reduce both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers and therewith the overall power consumption of the modulator. Additional it will be shown that the proposed concept is suitable for very low supply voltages. The DAC architecture was exemplary implemented in a second-order 2MHz CT /spl Sigma//spl Delta/ modulator for UMTS applications operating at a sample frequency of 50MHz. The modulator operates from a single 1.8V power supply and achieves a 11-bit dynamic range for the 2MHz passband.

This paper deals with specification and design methodology of analog to digital converter (ADC) stage for high dynamic range wide band multistandard radio receiver. To respect high resolution requirements a sigma-delta (/spl Sigma//spl Delta/) modulator based ADC is proposed. A high dynamic range low complexity 1-bit sigma-delta modulator is designed to guarantee high linearity for GSM/UMTS signals. Hence, a novel stable 3/sup rd/ order 1-bit low-pass /spl Sigma//spl Delta/ modulator is defined. Simulation results show more than 90 dB dynamic ranges for GSM and 60 dB for UMTS.

A new verification technique for /spl Delta//spl Sigma/ analog-to-digital converters (ADC) is proposed. The ADC is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistor-level simulation data. Non-idealities in circuit behavior are captured by the adaptive regression technique from the collected data. The algorithms have been implemented in a simulation program ARSIM (Adaptive Regression Simulator), which performs data sampling, model building, and simulation. Experimental results using ARSIM are shown on a second-order /spl Delta//spl Sigma/ modulator, and they demonstrate the effectiveness of our technique as a fast and accurate approach for verifying /spl Delta//spl Sigma/ converters.

Given an integer /spl sigma/>1, a vector (/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/), of nonnegative integers, and an undirected graph G=(V, E), an L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring of G is a function f from the vertex set V to a set of nonnegative integers, such that |f(u)-f(v)|/spl ges//spl delta//sub i/, if d(u,v)=i, for 1<i<(/spl sigma/-1), where d(u, v) is the distance (i.e., the minimum number of edges) between the vertices u and v. An optimal L(/spl delta//sub 1/, /spl delta//sub 2/,..., /spl delta//sub /spl sigma/-1/)-coloring for G is one using the smallest range /spl lambda/ of integers over all such colorings. This problem has relevant application in channel assignment for interference avoidance in wireless networks, where channels (i.e., colors) assigned to interfering stations (i.e., vertices) at distance i must be at least /spl delta//sub i/ apart, while the same channel can be reused in vertices whose distance is at least /spl sigma/. In particular, two versions of the coloring problem - L(2, 1, 1) and L(/spl delta//sub 1/, 1,..., 1) - are considered. Since these versions of the problem are NP-hard for general graphs, efficient algorithms for finding optimal colorings are provided for specific graphs modeling realistic wireless networks, including rings, bidimensional grids, and cellular grids.

Design equations and experimental results for a second-order delta-sigma (/spl Sigma/-/spl Delta/) based infinite impulse response (IIR) filter are presented. Although input and output signals are analog, filtering is performed directly on an oversampled /spl Delta/-/spl Sigma/ modulated signal, thus eliminating the need for any decimation or interpolation filters. Circuit complexity consists of only a single /spl Delta/-/spl Sigma/ analog-digital (A/D) modulator, approximately ten 26-b adders, a 1-b digital-analog converter (D/A) and a low-pass filter. It is shown experimentally that such a filtering technique can realize filter pole-Q's of at least 2600 in the audio frequency range. >

Sigma-delta (/spl Sigma/-/spl Delta/) modulators are used as a robust means of providing high-linearity analog-digital and digital-analog conversion. For first-order /spl Sigma/-/spl Delta/ modulators, idle channel conditions which produce colored quantization noise have been considered the only inherent limitation where, even for highly periodic inputs, harmonic distortion dominates the quantizer error in the output of first-order /spl Sigma/-/spl Delta/ modulators. This places an inherent limit on the achievable performance of such devices, irrespective of the state-of-the-art in implementation. >

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.

Let /spl delta//sub /spl Sigma// be a measure of the relative stability of a stable dynamical system /spl Sigma/. Let /spl tau//sub A(/spl Sigma//) be a measure of the computational efficiency of a particular algorithm A which verifies the stability property of /spl Sigma/. For two representative cases of /spl Sigma/, we demonstrate the existence of a particular measure /spl delta//sub /spl Sigma// and an algorithm A such that, /spl delta//sub /spl Sigma///spl tau//sub A(/spl Sigma//)=c where c depends possibly on the dimension of the system /spl Sigma/ and parameters which are specific to the algorithm A, but independent of any other system characteristics. In particular, given /spl Sigma/ and A, one can estimate /spl delta//spl Sigma/ by measuring /spl tau//sub A(/spl Sigma//).

The design of a delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order /spl Delta//spl Sigma/ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption.

This paper describes a new sigma-delta (/spl Sigma/-/spl Delta/) frequency synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an automatic calibration circuit which tunes the phase-locked loop (PLL) response to compensate for process tolerance and temperature variation. The availability of this new calibration method allows the use of precompensation techniques to achieve high data rate modulation without requiring factory calibration. The calibration method can be applied to GFSK/GMSK modulation and also M-ary FSK modulation. The PLL, including 1.8-GHz voltage controlled oscillator (VCO), /spl Sigma/-/spl Delta/ modulator, and automatic calibration circuit, has been implemented in a 0.6-/spl mu/m BiCMOS integrated circuit. The test chip achieves 2.5 Mb/s using GFSK and 5.0 Mb/s using 4-FSK.

This paper covers a general design guidelines, implementation issues as well as performance limitations of a clock-jitter insensitive multibit digital-to-analog converter (DAC) topology for high-performance low-power continuous-time /spl Sigma//spl Delta/ modulators. Since, the considered DAC building block uses a time-variant feedback pulse shape both the clock jitter influence as well as the slew rate and bandwidth requirements of the used amplifiers are reduced so that also the overall power consumption of the modulator is decreased. It will be shown that the proposed concept provides various benefits over the commonly used current-source DACs. Additionally, the influence of a number of circuit non-idealities is analytically determined and verified by behavioural simulations in order to minimize their impact on the modulator performance on the one hand and to optimize the overall power consumption on the other hand. In particular, the effects of clock jitter, random device mismatch, finite switch resistance, circuit noise as well as the limited output impedance is analyzed. Besides, the impact of amplifier confinements like finite DC-gain as well as gain-bandwidth are evaluated.

This paper presents an integrated 26-MHz digitally controlled crystal oscillator (DCXO) for GSM standard that achieves a phase noise of -140 dBc/Hz at 1 kHz and -152 dBc/Hz at 10 kHz offset. The measured supply pushing at 26 MHz is 0.5 ppm/V. Frequency tuning is done by a predistorted 14-bit MOS capacitor digital-to-analog converter (DAC) where the top 10 bits are thermometer coded and the bottom 4 bits are /spl Sigma//spl Delta/ modulated. Monotonicity of /spl sim/0.004 ppm/step across the entire /spl sim/70 ppm tuning range is guaranteed by applying a sliding /spl Sigma//spl Delta/ modulation to the last exercised thermometer element. This DCXO consumes 3 mW at 1.4 V supply and occupies 0.18 mm/sup 2/ in the 90-nm CMOS process.

Fourth-order cascade /spl Sigma//spl Delta/ modulators are very well suited for IC implementation using analog sampled-data circuits because of their robust, stable operation and their capability to achieve high resolution and wide bandwidth with moderate power consumption. However, their optimum realization requires careful consideration of their performance degradations due to the hardware nonidealities. This paper presents a comparative study of the influence of finite op-amp gain and capacitor mismatch on the performance of fourth-order cascade /spl Sigma//spl Delta/ modulators realized by means of switched-capacitor circuits. It considers single-bit and multibit quantizers and draws a number of comparative remarks validated by time-domain behavioral simulations.

A 64-MHz clock rate sigma-delta (/spl Sigma//spl Delta/) analog-to-digital converter (ADC) with -105-dB intermodulation distortion (IMD) at a 1.5-MHz signal frequency is reported. A linear replica bridge sampling network enables the ADC to achieve high linearity for high signal frequencies. Operating at an oversampling ratio of 29, a 2-1-1 cascade with a 2-b quantizer in the last stage reduces the quantization noise level well below that of the thermal noise. The measured signal-to-noise and distortion ratio (SNDR) in 1.1-MHz bandwidth is 88 dB, and the spurious-free-dynamic-range (SFDR) is 106 dB. The modulator and reference buffers occupy a 2.6-mm/sup 2/ die area and have been implemented with thick oxide devices, with minimum channel length of 0.35 /spl mu/m, in a dual-gate 0.18-/spl mu/m 1.8-V single-poly five-metal (SP5M) digital CMOS process. The power consumed by the ADC is 230 mW, including the decimation filters.