Timing Analysis of Concurrent Programs

Multithreaded programs are hard to develop and test. In order for programs to avoid unexpected concurrent behaviors at runtime, for example data-races, synchronization mechanisms are typically used to enforce a safe subset of thread interleavings. Also, to test multithreaded programs, devel- opers need to enforce the precise thread schedules that they want to test. These tasks are nontrivial and error prone.

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.

Stochastic perturbation finite elements

On the basis of the dynamics equation of Jeffcott rotor-stator model with imbalance, the random responses of rotor-stator systems with rubbing is studied. The method is based on a second order expansion of the governing equations and the matrix calculus, the Kronecker algebra is used in the mathematical development. The random parameters including shaft stiffness and damping, stator stiffness and damping, radial clearance and stator radial stiffness are used to research the random responses of the rotor-stator systems. The numerical results are also presented and discussed.

A numerical algorithm is called stable if an error, in all possible executions of the algorithm, does not exceed a predefined bound. Introduction of concurrency to numerical algorithms results in a significant increase in the number of possible computations of the same result, due to different possible interleavings of concurrent threads. This can lead to instability of previously stable algorithms, since rounding can result in a larger error than expected for some interleavings. Such errors can be very rare, since the particular combination of rounding can occur in only a small fraction of interleavings. In this paper, we apply the cross-entropy method -- a generic approach to rare event simulation and combinatorial optimization -- to detect rare numerical instability in concurrent programs. The cross-entropy method iteratively samples a small number of executions and adjusts the probability distribution of possible scheduling decisions to increase the probability of encountering an error in a subsequent iteration. We demonstrate the effectiveness of our approach on implementations of several numerical algorithms with concurrency and rounding by truncation of intermediate computations. We describe several abstraction algorithms on top of the implementation of the cross-entropy method and show that with abstraction, our algorithms successfully find rare errors in programs with hundreds of threads. In fact, some of our abstractions lead to a state space whose size does not depend on the number of threads at all. We compare our approach to several existing testing algorithms and argue that its performance is superior to other techniques.

Automatic finding of bugs in multithreaded programs is an important but inherently difficult task, even in the finite-state interleaving-semantics case. The complexity of this task has only been partially explored so far. We measure quantities such as the diameter, which is the longest finite distance realizable in the transition graph of the program, the local diameter, which is the maximum distance from any program state to any thread-local state, and the computational complexity of bugfinding. For the subclass of so-called binary multithreaded programs, we prove new bounds: all these quantities are majorized by a polynomial and, in certain cases, by a linear, logarithmic, or even constant function. Our bounds present a preparation step towards the corresponding polynomial-bound claims for general programs. These claims contrast sharply with the common belief that the main obstacle to analyzing concurrent programs is the exponential state explosion in the number of threads.

Pattern-based verification checks the correctness of program executions that follow a given pattern , a regular expression over the alphabet of program transitions of the form w 1 * … w n * . For multithreaded programs, the alphabet of the pattern is given by the reads and writes to the shared storage. We study the complexity of pattern-based verification for multithreaded programs with shared counters and finite variables. While unrestricted verification is undecidable for abstracted multithreaded programs with recursive procedures and PSPACE-complete for abstracted multithreaded while-programs (even without counters), we show that pattern-based verification is NP-complete for both classes, even in the presence of counters. We then conduct a multiparameter analysis to study the complexity of the problem on its three natural parameters (number of threads+counters+variables, maximal size of a thread, size of the pattern) and on two parameters related to thread structure (maximal number of procedures per thread and longest simple path of procedure calls). We present an algorithm that for a fixed number of threads, counters, variables, and pattern size solves the verification problem in st O ( lsp + ⌈ log ( pr +1) ⌉) time, where st is the maximal size of a thread, pr is the maximal number of procedures per thread, and lsp is the longest simple path of procedure calls.

With increasing density of power, traditional frequency scaling of processors came to an end. The power wall forced the industry to seek performance from parallel processing - shifting focus away from instruction throughput to thread throughput. This led to the development of multicore processors. However, extracting performance from multicore is not an easy problem. There are two approaches towards utilizing the multicores: scale-out parallelism that seeks performance by running independent threads and scale-up parallelism where multiple threads of a program execute in parallel to improve performance. In scale-out parallelism, the memory traffic increases linearly with the number of threads until the memory bandwidth is fully saturated at which point increasing the number of threads yield no benefit. Scale-up parallelism is contingent on programmers writing parallel software that takes advantage of the multicores - a task that fraught with perils. Data race in multithread programming is a well-known issue. What is less-known is that a majority of the resiliency and recovery solutions that have been developed for single cores do not scale for multicores.Reliability of processors is a major concern today. Catastrophic failures such as power loss can erase months of computation. System wide check-pointing provides a measure of protection against loss from such failures. Unfortunately, system wide check-pointing is not practical for errors that occur for individual threads, as such errors are far more prevalent today. Single event upsets (SEU) are caused by radiation-induced soft errors as well as timing errors that stem from signal integrity problems. Power supply noise caused either by circuit switching or power converters is a major source of such errors as are thermal issues and other sources of electrical noises. If a thread experiences an error, (i) we must have detection mechanisms in place as well as (ii) correction mechanisms. In general it is not possible to roll back a thread without rolling back inter-thread messages that may trigger cascading roll-backs of other threads. Such roll-backs result in wasted computation and wasted power.In this tutorial, we will explore this issue at depth and present state of the art industrial and academic solutions to address these problems. This tutorial also covers the resiliency trade-offs in modern processors that arise from increasing error-rates with decreasing supply voltage which is the preferred solution for reducing processor power that enables parallelism and multicores in the first place. We will explore multi-objective optimization problem that seek to satisfy dual objectives of performance-per-watt and lower error-rate. We will describe novel solutions for ensuring total store order (TSO) in processors in presence of errors. The tutorial presenters are academics with long experience in industry. They have studied these problems at-depth in their research. The tutorial is targeted for a wide audience and does not require attendees to be fully-versed in design or microarchitecture. The proposed tutorial will introduce the problem both qualitatively and quantitatively; discuss microarchitecture alternatives and trade-offs for resiliency. Although this tutorial primarily focuses on hardware sources of errors, it will touch upon programming errors, and debug support for identification of software bugs.

Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs by temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (set-associative LRU, locked, ACDC, etc.), most of the times adapting techniques designed to analyze instruction caches. On the other hand, there are methodologies to analyze the data reuse of a program, independently of the data cache. In this paper we propose a generic WCET analysis framework to analyze data caches taking profit of such reuse information. It includes the categorization of data references and their integration in an IPET model. We apply it to a conventional LRU cache, an ACDC, and other baseline systems, and compare them using the TACLeBench benchmark suite. Our results show that persistence-based LRU analyses dismiss essential information on data, and a reuse-based analysis improves the WCET bound around 17% in average. In general, the best WCET estimations are obtained with optimization level 2, where the ACDC cache performs 39% better than a set-associative LRU.

Accurate estimation of the worst-case execution time (WCET) of a program is important for real-time embedded software. Static WCET estimation involves program path analysis and architectural modeling. Path analysis is complex due to the inherent difficulty in detecting and exploiting infeasible paths in a program's control flow graph. In this paper, we propose an efficient method to exploit infeasible path information for WCET estimation without resorting to exhaustive path enumeration. We demonstrate the efficiency of our approach for some real-life control-intensive applications.

Worst case execution time (WCET) analysis is essential for exposing timeliness defects when developing hard real-time systems. However, it is too late to fix timeliness defects cheaply since developers generally perform WCET analysis in a final verification phase. To help developers quickly identify real timeliness defects in an early programming phase, a novel interactive WCET prediction with warning for timeout risk is proposed. The novelty is that the approach not only fast estimates WCET based on a control flow tree (CFT), but also assesses the estimated WCET with a trusted level by a lightweight false path analysis. According to the trusted levels, corresponding warnings will be triggered once the estimated WCET exceeds a preset safe threshold. Hence developers can identify real timeliness defects more timely and efficiently. To this end, we first analyze the reasons of the overestimation of CFT-based WCET calculation; then we propose a trusted level model of timeout risks; for recognizing the structural patterns of timeout risks, we develop a risk data counting algorithm; and we also give some tactics for applying our approach more effectively. Experimental results show that our approach has almost the same running speed compared with the fast and interactive WCET analysis, but it saves more time in identifying real timeliness defects.

Kronecker algebra has proven useful in analyzing multithreaded programs when semaphores are the only synchronization primitives. In contrast, Ada uses higher level synchronization primitives, namely protected objects. In this paper we show how Kronecker algebra can be generalized to statically analyze Ada multi-tasking programs that employ protected objects for synchronization issues.

For safety-critical real-time software, if worst-case execution time (WCET) violates a time constraint, it is considered having a timeliness defect. To fix the defect early with lower cost, a WCET optimization strategy is proposed based on source code refactoring. The strategy guides programmers to search refactoring opportunities in the correct positions and perform refactorings by a reasonable sequence. To this end, the worst-case execution path (WCEP) of a target program is firstly extracted from its control flow graph. Then the WCEP is mapped onto source code by the back-annotation technique. An abstract syntax tree-based invariant path identification algorithm is developed for recognizing the invariant paths from the source-level WCEP. According to the invariant paths and loop statements, the source code is divided into four optimization regions with different priorities. Thus the searching scopes are reduced, and invalid refactorings are avoided. On the basis, the refactoring which has the lowest cost in the same region is performed first. To support the strategy, a cost model of source code refactoring is designed. It mainly considers adverse effects of refactorings on the maintainability of source code. The experimental results showed that the optimization strategy reduced WCET effectively and maximally kept the maintainability. Therefore it is more suitable for WCET optimization in an early programming phase. It is helpful to fix the defects early and then guarantee the timeliness safety of the software.

The authors present co-transformation, a novel approach to the mapping of execution information from the source code of a program to the object code for the purpose of worst-case execution time (WCET) analysis. Their approach is designed to handle the problems introduced by optimizing compilers, i.e. that the structure of the object code is very different from the structure of the source code. The co-transformer allows one to keep track of how different compiler transformations, including optimizations, influence the execution time of a program. This allows one to statically calculate the execution time of a program at the object code level, using information about the program execution obtained at the source code level.

This paper explores the potential of quantum computing on a WCET(Worst-Case Execution Time (of a program).)-related combinatorial optimization problem applied to a set of several polynomial special cases. We consider the maximization problem of determining the most expensive path in a control flow graph. In these graphs, vertices represent blocks of code whose execution times are fixed and known in advance. We port the considered optimization problem to the quantum framework by expressing it as a QUBO. We then experimentally compare the performances in solving the problem of classic Simulated Annealing (SA), Quantum Annealing (QA), and Quantum Approximate Optimization Algorithm (QAOA). Our experiments suggest that QA represents a fast equivalent of simulated annealing. Indeed, we measured the approximation ratio on the results of QA and SA, showing that their performances are comparable, at least on our set of simplified problems.KeywordsWCETsQuantum computingQUBOCombinatorial optimizationQuantum annealingQAOA