Timing verification with the non-periodic gated clocking

Using constraint logic programming and relational interval arithmetic, as implemented in CLP (BNR) Prolog, we develop a simple yet complete method for interface timing verification. We show how the problems raised by timing verification (consistency, causality and compatibility) can be formulated as constraint satisfaction problems and solved using relational interval arithmetic when the timing constraints are of the linear, earliest or latest type; we examine the effect of correlation between timing delays (within their specified intervals) and show how an interval delay narrowing method can be applied in this context. The original contribution of this paper is to provide a unifying framework for interface timing verification and to present a method that allows delay correlation to be considered.

Embedded hard real-time systems need reliable guarantees for the satisfaction of their timing constraints. During the last years sophisticated analysis tools for timing analysis at the code-level, controller-level and networked system-level have been developed. This trend is exemplified by two tools: AbsInt’s timing analyzer aiT, and and Symtavision’s SymTA/S. aiT determines safe upper bounds for the execution times (WCETs) of non-interrupted tasks. SymTA/S computes the worst-case response times (WCRTs) of an entire system from the task WCETs and from information about possible interrupts and their priorities. A seamless integration between both tools provides for a holistic approach to timing validation: starting from a system model, a designer can perform timing budgeting, performance optimization and timing verification, thus covering both the code and the system aspects. However, the precision of the results and the efficiency of the analysis methods are highly dependent on the predictability of the execution platform. Especially on multi-core architectures this aspect becomes of critical importance. This paper describes an industry-strength tool flow for timing validation, and discusses prerequisites at the hardware level for ascertaining high analysis precision.

This paper presents an analysis of a sequential Triggered “Time Bomb” hardware Trojan (HT). Major security concerns have been rising up since malicious modification of hardware or fabrication IC can lead to an altered functional behavior, potentially with disastrous consequences in safety-critical applications. Due to the stealthy nature of the hardware Trojans the conventional design and time verification and post manufacturing testing cannot be readily extended. There are a large number of possible instances and operating modes for the hardware Trojans in a digital system. Since the hardware Trojan insertion can modify the functionality of the digital integrated circuit (IC), alter its behavior, generate denial of service (DoS), the HT threats should be analyzed with maximum importance through the entire lifecycle of the IC.

Quantum‐dot cellular automata (QCA) is a highly attractive alternative to CMOS for future digital circuit designs. The circuits in QCA have been extensively studied, which suffer from negative impacts due to the limits of the manual design process, even for a modest complexity. In the process of QCA circuit design, the problems caused by clock distribution and long transmission lines have to be considered. In order to solve such problems, some researchers have proposed several clock schemes and expected to realise electronic design automation. These clock schemes, however, have drawbacks; the most important one is the limitation of flexibility on designing complex circuits. In this regard, this study proposes a convenient, flexible, and efficient (CFE) clocking scheme by using diamond structures for clock zones, each of which has the same neighbouring clock zone and four information transmission directions. It has main advantages of existing clocking schemes and can commendably increase the flexibility in circuit design process. In order to show the suitability of the proposed CFE scheme using standard clock mechanism in QCA, several types of circuits proposed in this study reveal its advantages in comparison with an existing state‐of‐the‐art clocking scheme.

The increase in complexity of superconducting single flux quantum circuits enabled by the IARPA Cryogenic Computing Complexity project has highlighted the need for hardware description language (HDL) models that allow fast and reliable simulation and verification of such circuits. The design of new cell libraries for successive nodes of fabrication processes also exposed the cost of building new HDL models for each cell library. We expand an automatic HDL extraction method presented earlier to provide a fully automated tool for timing model extraction from an arbitrary cell the functionality of which does not need to be known. We describe in detail how models for the Verilog HDLs are constructed to allow timing verification and to implement delays as functions of bias, process tolerances, thermal noise, and load. Modeling of wire length delays is discussed, and results presented for complex circuits synthesized with new place-and-route algorithms.

A reliable timing verification methodology has been developed and proven on a 45nm SOI standard cell library. This methodology is currently used at more advanced process nodes.

This paper presents a formal method to verify execution time bounds of programs at the source level, where timing constraints along with other functional requirements are specified in the routines' contracts and are verified in a modular manner. The approach works based on a countdown time budget mechanism to guarantee the termination of the input program, and incorporates the concepts of separation logic, making it integrable with verification approaches for pointer-manipulating programs and applicable for concurrent programs where time resource needs to be passed among different threads. We selected the MSP430 microcontroller as well as a simple non-optimizing compiler as a case study and defined a co-inductive concrete semantics to model time consumption and potential non-termination of commands based on this platform. Accordingly, we developed the corresponding symbolic execution and proved that it is sound, i.e., if a program does not fail in the symbolic execution, then it respects the specified time bounds in the concrete execution too. Our preliminary results show that the proposed approach can be used to verify time bounds of programs involving separation logic based specifications.

As the most important daily management work in power application, electrical energy metering is carried out throughout the whole process of power production, transmission and use. Ensuring the accurate and reliable operation of electric energy measurement is the key to establish a fair, just and orderly electric power marketing market. At present, there are many problems in the inspection process of electric power measurement device, which include large workload, long verification time, sampling accuracy and algorithm performance constraints. In this paper, the remote on-line diagnosis of electrical energy metering decice is studied. Based on a large amount of sampling datas of power measurement, voltage and current, it introduces the parallel computing in data mining. Based on support vector machine, data and task parallelization fault diagnosis modelsare established,the online real-time monitoring and failure warning for electric power measurement device is realized, which contains abnormal characteristics and fault state. The visualization method is used to upload the device failure pictures in time and the diversified fault early warning technology is adopted, in order that the staff can timely analyze the electrical energy metering device in the fault or abnormal condition. In this way, the remote state monitoring and operation management level of the electrical energy metering device are improved.

Verification of real time embedded systems at high level of abstraction is a challenging task that requires the simulation of the system and the checking of its timing and functional properties as well as constraints. The paper presents a methodology which starts from UML sequence diagrams with MARTE timing constraints and generates a SystemC/TLM model with checkers. The execution of the model allows to verify the specified sequence of exchanged information between components while checkers allow to verify that properties and timing constraints are met. The application of the methodology to the design of a wireless sensor node shows the validity of the approach and its simulation overhead.

We present a symbolic simulation based verification approach which can be applied to large synchronous circuits. A new technique to encode the state and input constraints as parametric Boolean expressions over the state and input variables is used to make our symbolic simulation based verification approach efficient. The constraints which are encoded through parametric Boolean expressions can involve the Boolean connectives (·, +, ⌝), the relational operators (<, ≤, >, ≥, ≠, =), and logical connectives (∧, ∨). This technique of using parametric Boolean expressions vastly reduces the number of symbolic simulation vectors and the time for verification. Our verification approach can also be applied for efficient modular verification of large designs; the technique used is to verify each constituent sub-module separately, however in the context of the overall design. Since regular arrays are part of many large designs, we have developed an approach for the verification of regular arrays which combines formal verification at the high level and symbolic simulation at the low level(e.g., switch-level). We show the verification of a circuit called Minmax, a pipelined cache memory system, and an LRU array implementation of the least recently used block replacement policy, to illustrate our verification approach. The experimental results are obtained using the COSMOS symbolic simulator.

Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

Quantum dot cellular automata (QCA) technology is emerging as a future technology which designs the digital circuits at quantum levels. The technology has gained popularity in terms of designing digital circuits, which occupy very less area and less power dissipation in comparison to the present complementary metal oxide semiconductor (CMOS) technology. For designing the routers at quantum levels with non-blocking capabilities various multi-stage networks have been proposed. This manuscript presents the design of the N×N Clos switch matrix as a multistage interconnecting network using quantum-dot cellular automata technology. The design of the Clos switch matrix presented in the article uses three input majority gates (MG). To design the 4 × 4 Clos switch matrix, a basic 2 × 2 switch architecture has been proposed as a basic module. The 2 × 2 switching matrix (SM) design presented in the manuscript utilizes three input majority gates. Also, the 2 × 2 SM has been proposed using five input majority gates. Two different approaches (1&2) have been presented for designing 2 × 2 SM using five input majority gates. The 2 × 2 SM design based on three input majority gate utilizes four zone clocking scheme to allow signal transmission. Although, the clocking scheme used in 2 × 2 SM using three input MG and in 2 × 2 SM approach 1 using five input MG is conventional. The 2 × 2 SM approach 2 design, utilizes the clocking scheme in which clocks can be applied by electric field generators easily and in turn the switch element becomes physically realizable. The simulation results conclude that the 2 × 2 SM is suitable for designing a 4 × 4 Clos network. A higher order of input-output switching matrix, supporting more number of users can utilize the proposed designs.

The UML activity diagram language is the de facto language for behavioral modeling capable of block level modeling of real time multiprocessor SoC applications where timing behavior is a critical aspect. Although there are several tools for timing verification of logics with branching time semantics, there are no known model checkers for timing verification of logics with linear time semantics as needed for many verification tasks. This work deals with timing verification of UML activity diagram models of applications. We propose a subset of TPTL (timed prepositional temporal logic) for specifying timing queries. We develop an automata based model checker for verifying such queries. We present a comparison of the proposed timing verification with the state of the art for random test-cases.

This paper presents the issue of dynamic multi-level simulation of hardware designs that addresses the problem of inefficiency associated with the conventional static multi-level simulation ap proaches as in ADLIB-SABLE (Hill 1980), DIANA (Demou and Arnout 1979), and SPLICE (Newton 1978). In this approach, digital sim ulation or verification (McWilliams 1980) of hardware designs is initiated at a high level of abstraction. When detailed results are required for one or more high-level components or for tracing the source of an error to any of the lower-level devices, the appropriate components are expanded into their lower-level implementations. Then simulation or verification initiates at that level. Following completion of execution at the lower level, con trol returns to the higher level. Consequently, only those sub parts of a digital design are selected for expansion and detailed simulation that are dynamically warranted by the higher-level simulation results. Unnecessary simulation effort may be elimi nated. Dynamic multi-level simulation or zooming is a generaliza tion of the swapping technique (Szygenda 1973) to functional and fault simulation and timing verification and to the differ ent abstraction levels in the hierarchy between the gate- and behavior-levels. This paper also addresses the implementation of zooming in the rule-based design verifier, RDV (Ghosh 1984), at Stanford University. That RDV uses Ada (U.S. Dept. of Defense 1983) as a hardware description language and simulation envi ronment (Ghosh 1985).

In this paper, we implement the UDCM (up down conversion module) for the WiBro base station equipment RAS (radio access station). It performs the digital IF (intermediate frequency) signal processing between a channel card and the radio equipments (REs). The UDCM embed on digital optic interface unit of RAS. Converting the frequency into 10 MHz or baseband is the main function. It filters the spurious within channel bandwidth for downlink (DL) /uplink (UL). Also to support the communication with the other chips or peripherals, we design the interface modules and controller. As the UDCM is optimized on the Virtex5 families, it can save the dedicated FPGA resources and lowers the development costs. Its functionality is verified using simulation tools on the RTL (register transfer level) for the predefined test vector. After setting the timing constraints for the interface signals and timing verification, the UDCM downloaded into main unit. Finally, this digital unit is connected to a channel card and REs to ensure the expected performance for its reference simulation results by capturing I/Q, synchronization signals.