Tiny-Tail Flash

NAND flash memory has been widely adopted as the primary data storage medium in data centers. However, the inherent characteristic of out-of-place updates in NAND flash necessitates garbage collection (GC) operations on NAND flash-based solid-state drives (SSDs), aimed at reclaiming flash blocks occupied by invalid data. GC processes entail additional read and write operations, which can lead to the blocking of user requests, thereby increasing the tail latency. Moreover, frequent execution of GC operations is prone to induce more pages to be written, further reducing the lifetime of SSDs. In light of these challenges, we introduce an innovative GC scheme, termed SplitGC. This scheme leverages the records of data redundancy gathered during periodic read scrub operations within the SSD. By analyzing these features of data duplication, SplitGC enhances the selection strategy for the victim block. Furthermore, it bifurcates the migration of valid data pages into two phases: non-duplicate pages follow standard relocation procedures, whereas the movement of duplicate pages is scheduled during idle periods of the SSD. The experiment results show that our scheme reduces tail latency induced by GC by 8% to 83% at the 99.99th percentile and significantly decreases the amount of valid page migration by 38% to 67% compared with existing schemes.

Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile memory technologies, such as NAND flash memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND flash memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on flash memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of flash memory. Moreover, because flash memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of flash memory space and to prolong the flash memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of flash memory management in various application scenarios. The future development trends of flash memory, such as the widespread adoption of higher-level flash memory and the emerging of three-dimensional (3D) flash memory architectures, are also discussed.

Long-tail latency values significantly affect the user experience and hence they are a major concern in modern systems. However, tail latency characteristics of applications developed using microservices architecture are still unknown. In this paper, we focus on analyzing and characterizing the behaviour of tail latency values of microservices workloads under service's peak sustainable throughput with a closed system model. Our particular focus is to investigate the impact of heap size, garbage collection, concurrency and service demand on the tail latency. Our study has two parts. First, we develop and experiment on four microservices micro benchmarks representing CPU bound, network I/O bound, memory bound and database I/O bound to find the tail characteristics under different concurrency, heap, service demand and garbage collector. Then, in the second part, we explore the tail latency characteristics identified on micro benchmarks by testing those conditions using standard microservices benchmark application, Socks Shop. We observe first that microservices latency distributions exhibit the power law behavior. Second, we systematically prove that microservices workload distributions do not exhibit the heavy tailed behavior. We show that increasing the level of concurrency and service demand increases the tail latency. We use queuing simulation to prove our claims. Finally, we show that tail latency values of memory bound and database I/O bound microservices workloads are correlated with heap size and garbage collection.

Solid State Drives (SSDs) have replaced magnetic disks in many application areas, as they provide very high performance for arbitrary access patterns. Nevertheless, data written to a physical page has to be erased before a page can be rewritten. The corresponding garbage collection (GC) process can only be performed on a block granularity, where a block includes many pages, impacting both the performance and lifetime of an SSD. The cost of a GC process is typically measured in terms of its write amplification, i.e., the number of blocks internally written by the SSD divided by the number of write requests of the host.Several GC heuristics have been proposed to optimize the write amplification of SSDs. These heuristics have been mostly empirically evaluated, while no thorough theoretical results are available on the optimality of GC algorithms even for seemingly simple cases like uniform and independent access distributions.In this work, we theoretically investigate the GREEDY GC strategy for uniformly independently distributed write accesses. We therefore model the garbage collection process on SSDs as a stochastic process and prove that the expected write amplification incurred by the GREEDY GC strategy is at most that of any other online GC strategy.

As the flash memory performance increases with more bandwidth, the flash memory channel or the interconnect is becoming a bigger bottleneck to enable high performance SSD system. However, the bandwidth of the flash memory interconnect is not increasing at the same rate as the flash memory. In addition, current flash memory bus is based on dedicated signaling where separate control signals are used for communication between the flash channel controller and the flash memory chip. In this work, we propose to exploit packetized communication to improve the effective flash memory interconnect bandwidth and propose packetized SSD (pSSD) system architecture. We first show how packetized communication can be exploited and the microarchitectural changes required. We then propose the Omnibus topology for flash memory interconnect to enable a packetized network SSD (pnSSD) among the flash memory – a 2D bus-based organization that maintains a “bus” organization for the interconnect while enabling direct communication between the flash memory chips. The pnSSD architecture enables a new type of garbage collection that we refer to as spatial garbage collection that significantly reduces the interference between I/O requests and garbage collection. Our detailed evaluation of pnSSD shows 82% improvement in I/O latency with no garbage collection (GC) while improving I/O latency by 9.71× when GC occurs in parallel with I/O operation, through spatial garbage collection.

Garbage collection (GC) in NAND flash can significantly decrease I/O performance in SSDs by copying valid data to other locations, thus blocking incoming I/O requests. To help improve performance, NAND flash utilizes various advanced commands to increase internal parallelism. Currently, these commands only parallelize operations across channels, chips, dies, and planes, neglecting the block level due to risk of disturbances that can compromise valid data by inducing errors. However, due to the triple-well structure of the NAND flash plane architecture, it is possible to erase multiple blocks within a plane, in parallel, without diminishing the integrity of the valid data. The number of page movements due to multiple block erases can be restrained so as to bound the overhead per GC. Moreover, more capacity can be reclaimed per GC which delays future GCs and effectively reduces their frequency. Such an Intra-Plane Parallel Block Erase (IPPBE) in turn diminishes the impact of GC on incoming requests, improving their response times. Experimental results show that IPPBE can reduce the time spent performing GC by up to 50.7% and 33.6% on average, read/write response time by up to 47.0%/45.4% and 16.5%/14.8% on average respectively, page movements by up to 52.2% and 26.6% on average, and blocks erased by up to 14.2% and 3.6% on average. An energy analysis conducted indicates that by reducing the number of page copies and the number of block erases, the energy cost of garbage collection can be reduced up to 44.1% and 19.3% on average.

More and more embedded systems are emerging based on managed language runtime systems using garbage collected languages such as Java, Python, or the .NET language family. Furthermore, the garbage collection (GC) process is a bottleneck in an embedded system, effectively blocking most other processes including mutator memory access, responding to inputs, or asserting outputs. We demonstrate a valuable new heap memory architecture for garbage collected embedded systems, which works by creating a direct path between memory modules to achieve a two-fold speedup for a memory copy operation as compared to a baseline scenario using multiplexed shared address- and databusses. This direct-path memory setup is generalisable, and memory modules will continue to work as expected when not engaged in garbage collection. The solution space is evaluated by simulating GC activity extracted from the Elephant Track GC tracer. One particular solution is also implemented in hardware to demonstrate the practical realisation of the direct fast copy architecture.

With the advent of new flash-based memory technologies with ultra-low latency, directly applying inline data deduplication in flash-based storage devices can degrade the system performance since key deduplication operations lie on the shortened critical write path of such devices. To address the problem, we propose a Content-Aware Garbage Collection scheme (CAGC), which embeds the data deduplication into the data movement workflow of the Garbage Collection (GC) process in ultra-low latency flash-based SSDs. By parallelizing the operations of valid data pages migration, hash computing and flash block erase, the deduplication-induced performance overhead is alleviated and redundant page writes during the GC period are eliminated. To further reduce data writes and write amplification during GC, CAGC separates and stores data pages in different regions based on their reference counts. The performance evaluation of our CAGC prototype implemented in FlashSim shows that CAGC significantly reduces the number of flash blocks erased and data pages migrated during GC, leading to improved user I/O performance and reliability of ultra-low latency flash-based SSDs.

A ferroelectric (Fe)-NAND flash memory with a batch write algorithm and a smart data store to the nonvolatile page buffer is proposed. An enterprise solid-state drive (SSD) for a data center is a future promising market of NAND flash memories. The critical problem for such an enterprise SSD is a slow random write. The write unit in a NAND flash memory is a page, 4-8 KBytes. Because the minimum write unit of the operating system is a sector, 512 Bytes, a random write to write a smaller data than a page size frequently happens, which creates a garbage. As a garbage accumulates, a garbage collection is performed to increase a workable memory capacity. The garbage collection takes as much as 100 ms, which is 100 times longer than a page program time, 800 μs, and thus causes a serious performance degradation. In the proposed Fe-NAND flash memory, the data fragmentation in a random write is removed by introducing a batch write algorithm where a page buffer in the Fe-NAND flash memory temporarily stores a program data. The memory cell program starts after the program data as much as the page size accumulates in page buffers. As the data fragmentation is eliminated, the SSD performance can double. In addition, the nonvolatile page buffer realizes a power-outage-immune highly reliable operation. With a low program/erase voltage of 6 V and a high endurance of 100 million cycles, the proposed Fe-NAND flash memory is most suitable for a highly reliable highspeed low-power data-center-application enterprise SSD.

Cloud computing platforms enable applications to offer low-latency services to users by deploying data storage in multiple geo-distributed data centers. In this paper, through benchmark measurements on Amazon AWS and Microsoft Azure together with an analysis of a large-scale dataset collected from a major cloud CDN provider, we identify the high tail latency problem in cloud CDNs, which can substantially undermine the efficacy of cloud CDNs. One crucial idea to reduce the tail latency is to send requests in parallel to multiple clouds in cloud CDNs. However, since application providers often have a budget for using cloud services, deciding how many chunks to download from each cloud and when to download chunks in a cost-efficient manner still remain as open problems in our concerned scenario. To address the problem, we present TailCutter, a workload scheduling framework that aims at optimizing the tail latency while meeting cost constraints given by application providers. Specifically, we formulate the tail latency minimization (TLM) problem in cloud CDNs and design the receding horizon control based maximum tail minimization algorithm (RHC-based MTMA) to efficiently solve the TLM problem in practice. We implement TailCutter across multiple data centers of Amazon AWS and Microsoft Azure. Extensive evaluations using a large-scale real-world data trace (collected from a major ISP) illustrate that TailCutter can reduce up to 58.9% of the 100th-percentile user-perceived latency, as compared with alternative solutions under the cost constraint.

Recent advancements in flash-based solid state drive (SSD) make it a highly desirable storage device, especially for data-intensive applications. There are significant more SSDs used in data centers and high performance computing systems. SSDs perform one or two orders better than traditional hard disk drives generally. However, the performance of random writes on SSDs, especially small random writes, is still largely limited due to the garbage collection (GC) process. Existing work tried to utilize the on-device RAM as a write cache to improve the write performance, however directly utilizing it as a normal write cache under utilizes the RAM cache. In this poster, we present our initial study of a cache management scheme that hides the GC latency.

Bit-alterable flash-based SSDs, offering page-level erase operation, allows individual flash pages in a block to be erased independently. The page-level erase operation alleviates the overhead of page migration during garbage collection and improves the SSD lifetime. However, when the number of invalid pages within a block exceeds a certain threshold, the latency of page-level garbage collections using page-level erase may exceed that of block-level garbage collections. In bit-alterable flash memory, existing garbage collection strategies dynamically choose between page-level and block-level garbage collections based on their latency. This often fails to fully exploit the advantage of page-level garbage collection in reducing write amplification under low-load conditions.To address this limitation, we propose an adaptive garbage collection strategy called AGCB to dynamically adjust garbage collection operations by the runtime workload of flash channels, thereby enhancing SSD performance and lifetime. Specifically, AGCB classifies flash channels as busy or idle by monitoring the depth of the transaction queue in cache. According to this classification, AGCB selectively applies page-level or block-level garbage collection operations, aiming to minimize the impact of garbage collections with host I/O requests. Meanwhile, we introduce a staged victim block selection scheme to further improve garbage collection efficiency and wear leveling. The experimental results unveil that compared with the existing schemes, AGCB reduces the number of garbage collection operations, average response time, and blocked user requests by an average of 14.6%, 14.7%, and 17.3%, respectively.

In recent years, flash memory has become more widely used due to its advantages, such as fast data access, low power consumption, and high mobility. However, flash memory also has drawbacks that need to be overcome, such as erase-before-write, and the limitations of block deletion. In order to address this issue, the FTL (Flash Translation Layer) has been proposed with useful functionalities like address mapping, garbage collection, and wear-leveling. During the process of using, the data may be lost on power failure in the storage systems. In some systems, the data is very important. Thus recovery of data in the event of the system crash or a sudden power outage is of prime importance. This problem has attracted attention from researchers and many studies have been done. In this paper, we investigate previous studies on data recovery for flash memory from FTL processing solutions to PLR (Power Loss Recovery) solutions that have been proposed by authors in the conference proceeding, patents, or professional journals. This will provide a discussion of the proposed solutions to the data recovery in flash memory as well as an overview.

In last few decades' garbage management has become a perilous matter in the developing country along with the rapid growth in the population and pollution. In India, like other developing countries, garbage management has been ignored in many places and thus there is need of some effective solution. In most of the areas it is revealed that overflowed garbage bins are not emptied on time thus creating disease-ridden environment and infirm countries. Collection of garbage in bins faces daily variation in time as well as quantity. Waste picking vehicles of Municipal Corporation which are at fixed intervals has dwindling reliability and unmonitored collection system. In today's scenario the fuel and time consumed by the conventional system is more. The proposed model makes an IOT based smart garbage monitoring system which can detect the garbage level of the dustbin and via Wi-Fi and GSM the status and location of bins can be displayed on web server. This system will improve the coordination between the garbage collection and transportation process. The main aim of the model is to manage garbage through GPS and GSM technologies, used for tracking the vehicle and IR sensors, to identify the status of bins, if it is filled or empty.

Increasing use of NAND flash in newer application domains has been possible due to lowering cost per GB, consumer demands for storage and advantages of NAND flash over traditional disks. However, NAND flash has its idiosyncrasies resulting in asymmetric read/write times due to garbage collection and wear leveling requirements. Such asymmetric (non-deterministic) read/write times poses a challenge for the adoption of NAND flash in real-time systems. We present the implementation details of a flash translation layer called GFTLthat guarantees strict upper bounds on read/write times that are comparable to a theoretical ideal case. Such guarantees are made possible by dividing the source of non-determinism into deterministic intervals using our proposed approach called partial block cleaning. Using partial block cleaning, the process of garbage collection is divided into several smaller, deterministic steps. Partial block cleaning comes with an overhead of additional space requirements. We provide a proof on the limit of the additional space requirements.