Towards code generation from design models for embedded systems on heterogeneous CPU-GPU platforms

Heterogeneous computing platforms with multicore central processing units (CPUs) and graphics processing units (GPUs) are of increasing interest to designers of embedded signal processing systems since they offer the potential for significant performance boost while maintaining the flexibility of software-based design flows. Developing optimized implementations for CPU-GPU platforms is challenging due to complex, inter-related design issues, including task scheduling, interprocessor communication, memory management, and modeling and exploitation of different forms of parallelism. In this paper, we present an automated, dataflow based, design framework called DIF-GPU for application mapping and software synthesis on heterogeneous CPU-GPU platforms. DIF-GPU is based on novel extensions to the dataflow interchange format (DIF) package, which is a software environment for developing and experimenting with dataflow-based design methods and synthesis techniques for embedded signal processing systems. DIF-GPU exploits multiple forms of parallelism by deeply incorporating efficient vectorization and scheduling techniques for synchronous dataflow specifications, and incorporating techniques for streamlining interprocessor communication. DIF-GPU also provides software synthesis capabilities to help accelerate the process of moving from high-level application models to optimized implementations.

Automatic code generation for production automotive powertrain applications introduces many challenges for the tool vendor. Resource efficiency, reliability, and product process development issues need to be addressed. Automatic code generation used for rapid prototyping systems usually will not satisfy the requirements necessary for production oriented code generation. Some of the requirements critical to automatic code generation are not immediately obvious to a tool vendor who is not active in the user's industry. The purpose of this paper is to address some of the most common requirements for production automotive powertrain code generation.

The low-code approach is an important area of research being developed to improve the rapid creation and performance of software applications. This approach allows developers and users to easily create software applications through an interactive interface. Existing research shows that the low-code approach accelerates the development process in innovative ways, saves effort and time, and reduces code complexity. This study analyses and compares automatic code generation and transformation techniques in low-code platforms. The study analyses the contributions of automatic code generation and transformation to software engineering processes and evaluates the impact of these techniques on software product quality and development speed. The importance of the Model-Based Development (MBD) approach in automated code generation processes is highlighted. It is stated that MBD provides benefits such as speeding up the software development process and reducing errors by enabling automatic code generation from high-level abstract models. In the study, various literature studies were evaluated to examine the impact of automatic code generation and transformation techniques on the application development process. These studies have shown how automatic code generation and transformation techniques are applied, what results are achieved and what contributions these techniques make to the software development process. The results of the study show that automatic code generation and transformation techniques have a great impact on the application development process. In particular, the acceleration of the software development process, the reduction of errors and the ability to produce more effective and efficient software products are important benefits of these techniques. In addition, it has been found that this approach increases the success of software projects by enabling software developers to produce fast and accurate solutions in complex systems. In this context, the importance of automatic code generation and transformation techniques plays an important role in software development processes.

Analytical performance estimation during code generation on modern GPUs

The deployment of a client–server-based distributed intelligent system involves application development in both the network domain and the device domain. In the network domain, an application server (typically in the cloud) is deployed to execute the network applications. In the device domain, several Internet of Things (IoT) devices may be configured as, for example, wireless sensor networks (WSNs), and interact with each other through the application server. Developing the network and the device applications are tedious tasks that are the major costs for building a distributed intelligent system. To resolve this issue, a low-code or no-code (LCNC) approach has been purposed to automate code generation. As traditional LCNC solutions are highly generic, they tend to generate excess code and instructions, which will lack efficiency in terms of storage and processing. Fortunately, optimization of automated code generation can be achieved for IoT by taking advantage of the IoT characteristics. An IoT-based distributed intelligent system consists of the device domain (IoT devices) and the network domain (IoT server). The software of an IoT device in the device domain consists of the Device Application (DA) and the Sensor Application (SA). Most IoT LCNC approaches provide code generation in the network domain. Very few approaches automatically generate the DA code. To our knowledge, no approach supports the SA code generation. In this paper, we propose DeviceTalk, an LCNC environment for the DA and the SA code development. DeviceTalk automatically generates the code for IoT devices to speed up the software development in the device domain for a distributed intelligent system. We propose the DeviceTalk architecture, design and implementation of the code generation mechanism for the IoT devices. Then, we show how a developer can use the DeviceTalk Graphical User Interface (GUI) to exercise LCNC development of the device software.

Automated code generation has revolutionized software development, enabling developers to accelerate project timelines and reduce manual coding errors significantly. As reliance on these technologies grows, the inherent weaknesses of generated code become increasingly apparent. Recent studies have shown that code produced by AI is not inherently safer or of higher quality than human-written code, often replicating existing vulnerabilities. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">To this end, we propose SECURECODER, which integrates Retrieval-Augmented Generation (RAG) with Common Weakness Enumeration (CWE). SECURECODER first utilizes the advanced reasoning capabilities of large language models (LLMs) to generate natural language descriptions of the code’s core business logic and functionality. Then, from a semantic perspective, it matches the requirements of the code generation task with the CWE descriptions through a multi-label classification process. Finally, based on the matched CWE, SECURECODER generates a list of security guidelines the code generation model must adhere to. Breaking down end-to-end code generation tasks into single-target tasks that LLMs excel at ensures that the generated code not only meets functional requirements but also adheres to best security practices, thereby enhancing the interpretability of the automated code generation process. After evaluating 2 programming languages and 7 LLMs on Coploit-generated code, SECURECODER has great generalization capability and could be applied to more programming languages and vulnerability types. SECURECODER could significantly decrease the security weakness in the AI-generated code and is able to mitigate more than 65% of vulnerabilities exposed to software developers. Compared to the baseline open-source LLMs, code vulnerabilities were reduced by at least 14% and the code business logic was not affected.

SummaryThe execution of agent‐based simulations (ABSs) on hardware accelerator devices such as graphics processing units (GPUs) has been shown to offer great performance potentials. However, in heterogeneous hardware environments, it can become increasingly difficult to find viable partitions of the simulation and provide implementations for different hardware devices. To automate this process, we present OpenABLext, an extension to OpenABL, a model specification language for ABSs. By providing a device‐aware OpenCL backend, OpenABLext enables the co‐execution of ABS on heterogeneous hardware platforms consisting of central processing units, GPUs, and field programmable gate arrays (FPGAs). We present a novel online dispatching method that efficiently profiles partitions of the simulation during run‐time to optimize the hardware assignment while using the profiling results to advance the simulation itself. In addition, OpenABLext features automated conflict resolution based on user‐specified rules, supports graph‐based simulation spaces, and utilizes an efficient neighbor search algorithm. We show the improved performance of OpenABLext and demonstrate the potential of FPGAs in the context of ABS. We illustrate how co‐execution can be used to further lower execution times. OpenABLext can be seen as an enabler to tap the computing power of heterogeneous hardware platforms for ABS.

. This paper presents a multi-language and multi-environment generation of nonlinear finite element codes. The system consists of two major components. The Mathematica package AceGen is used for the symbolic derivation of formulae needed in numerical procedures and automatic code generation. The Computational Templates package is a collection of prearranged modules for the automatic creation of the interface between the finite element code and the finite element environment. The AceGen and the Computational Templates packages together enable multi-language and multi-environment generation of nonlinear finite element codes from the same symbolic description. The approach implemented in AceGen avoids the usual problem of uncontrollable growth of expressions by combining several techniques: symbolic and algebraic capabilities of Mathematica, an automatic differentiation technique, automatic code generation, simultaneous optimization of expressions; and theorem proving by stochastic evaluation of the expressions.

The model-based approach has been widely applied to the design of software. However, most of these approaches depend on simulation and manual code implementation, which reduces the efficiency and quality of software. In this paper, we present a new model-based approach, which automatically generates the executable C++ code running on the popular Robot Operation System (ROS). Our approach consists of three phases: modeling, verification, and automatic code generation. In the modeling phase, the internal interaction behaviors of robot systems are modeled as a network of timed automata. In the verification phase, the safety requirements are formalized and verified. In the code generation phase, a code generation tool can generate executable C++ code from the verified timed automata model. It bridges the gap between the formal model and the error-prone system implementation. Compared with existing method, the code generator provides the abstractions and mapping of ROS instructions, which realize the seamless connection between the generated code and ROS. The tool also supports most of the complex structures and advanced features of timed automata such as timer, committed location, and synchronous action. For evaluation, a real-industrial robot application of grasping a cup is conducted using our model-based design method, and the generated code can be directly deployed and successfully accomplishes the grasping task.

UML is an industry standard abstraction language, which encompasses a wide range of structural and behavioural diagrams. It reduces the gap between the functional requirements and system design phase of the software development process. Automated code generation from UML reduces development time and enables effective communication between managers and developers. Our tool exploits the one to one mapping between structural diagrams and object oriented code. Behavioural diagrams like activity, sequence and state diagrams are merged into a single structural diagram for code generation. The UML design diagrams are converted to platform independent textual representation, XML Metadata Interchange (XMI). The XMI parser generates an abstract syntax tree (AST). A template matching algorithm is used to convert the AST to the Java code. The tool also enables code generation in a phased manner to implement and verify the features of each diagram. The evaluation of the tool is shown using a case study and the results are compared with existing open source code generation tools. The generated OO code is functional and executable.

This chapter demonstrates how high-level code is automatically generated for multi-core processors. The code generation capability of the Verifiable Embedded Real-Time Application Framework (VERTAF) was extended to support multi-core processors in the new VERTAF/Multi-Core (VMC) framework for embedded systems. After users specify embedded software requirements via SysML models along with parallel task, parallel data, and parallel dataflow specifications, the code generator automatically generates parallel code. Using the digital video recording (DVR) system as a case study, we show the correctness and advantages of the VMC code generator. The main inputs of VMC code generator include the block definition diagrams, state machine diagrams, and requirement diagrams of the system to be designed. The proposed code generation in VMC not only significantly decreases the amount of manually-written code, but also provides a formal procedure for model-conforming code generation of multi-core embedded software.

Automatic code generation has been around for a long time, and the core technologies used are constantly evolving. Around application development work in the demand for high quality code generated rapidly, this paper proposes a automatic code generation method based on sequence generative adversarial network, the method adopts the adversarial learning thought, using LSTM as a generator, CNN as a discriminator, both through against each other to generate higher quality code samples. Experiment results show that this method can generate code automatically at the second level, and is significantly better than the existing methods in terms of generation rate and accuracy, which explores a new way of automatic code generation.

Model-Based Development (MBD) provides an additional level of abstraction, the model, which lets engineers focus on the business aspect of the developed system. MBD permits automatic treatments of these models with dedicated tools like synthesis of system's application by automatic code generation. Real-Time and Embedded Systems (RTES) are often constrained by their environment and/or the resources they own in terms of memory, energy consumption with respect to performance requirements. Hence, an important problem to deal with in RTES development is linked to the optimization of their software part. Although automatic code generation and the use of optimizing compilers bring some answers to application optimization issue, we will show in this paper that optimization results may be enhanced by adding a new level of optimizations in the modeling process. Our arguments are illustrated with examples of the Unified Modeling Language (UML) state machines diagrams which are widely used for control aspect modeling of RTES. The well-known Gnu Compiler Collection (GCC) is used for this study. The paper concludes on a proposal of two step optimization approach that allows reusing as they are, existing compiler optimizations.

Edge computing enables lower latency and secure real-time processing for machine learning (ML) workloads. State-of-the-art edge platforms are heterogeneous systems with compute cores of diverse performance and energy capabilities. This diversity motivates the need to identify the strengths of individual compute cores for more informed heterogeneous implementations of workloads. In this study, we benchmark a state-of-the-art heterogeneous platform consisting of a multicore CPU, integrated GPU and NPU, on its performance on various ML workloads. We measure system performance in terms of latency, throughput, and Energy-Delay Product (EDP) to analyze the performance-energy tradeoffs of such systems across various configurations -independently on the CPU, GPU or NPU and a heterogeneous NPU-GPU configuration. Our results indicate the superiority of NPUs for energy-efficient inference of LLMs and CNNs. We find that the NPU offers up to 5.2× speedup over CPU for CNN inference. For LLM inference, the NPU achieves up to 4× speedup during the prefill stage, while the GPU offers a 22× speedup on the decode stage. We observe that hybrid NPU-GPU implementation of LLM inference is superior to CPU-only inference in terms of energy consumption and end-to-end (E2E) latency, with an EDP decrease of about 93%. We highlight the broader applicability of our results by discussing extensions to long-context inference in causal LLMs and emerging state-space models on heterogeneous platforms.

Automatic data exchange among computer applications in industrial domains is an issue that has been largely worked out by the scientific and industrial community during last years. In the scope of the several industrial activities, the lack of tools and structured data models ready to be adopted to enable immediate connection of applications in networked-based environments is one of the main gaps identified when seeking global integrated solutions. ISO TC184/SC4 standards (e.g. STEP and PLib) seem ready to aid solving this problem, and the adoption of such standards has been opening new possibilities in this area, fulfilling most of the identified requirements. To support those standards, applications must be prepared with suitable mechanisms and interfaces easily adaptable for fast and reliable plug-and-play in the standard-based architecture, to accomplish the foreseen Open Platforms. Therefore, data modelling, data share and exchange, reuse of models, automatic code generators and software libraries, together with the possibility to incorporate expertise and knowledge representation, is a challenge to face when working in environments supported by heterogeneous platforms and concepts, as is the case. Nevertheless, to include mechanisms for conformance testing will faster assure interoperability among the applications joining the platform. The content of this paper intends to provide a broad view of two of the main ISO TC184/SC4 Standards, i.e. ISO 10303-STEP and ISO 13584-PLib, presenting their methodology and architecture, and contributing for a reference to those managing in the area of the integration of data in industrial domains. This text is based on the standard documentation available, and results from the work developed and in progress in the scope of some industrial and research international projects for the furniture and building and construction industrial sectors within CEN/ISSS and ISO TC184/SC4 (e.g. funStep and ECOS ESPRIT projects).