Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC

We investigate a domain decomposition method (DDM) of finite element method (FEM) using Intel's many integrated core (MIC) architecture in order to determine the most effective MIC usage. For this, recently introduced high-scalable parallel method of DDM is first introduced with a detailed procedure. Then, the Intel's Xeon Phi MIC architecture is presented to understand how to apply the parallel algorithm into a multicore architecture. The parallel simulation using the Xeon Phi MIC has an advantage that traditional parallel libraries such as the message passing interface (MPI) and the open multiprocessing (OpenMP) can be used without any additional libraries. We demonstrate the DDM using popular libraries for solving linear algebra such as the linear algebra package (LAPACK) or the basic linear algebra subprograms (BLAS). Moreover, both MPI and OpenMP are used for parallel resolutions of the DDM. Finally, numerical parallel efficiencies are validated by a two-dimensional numerical example.

A variable length Fast Fourier Transform (FFT) module is proposed in this paper, which can perform all the lengths of the Long Term Evolution (LTE) standard with high efficiency. Although the hardware complexity of the proposed scheme is slightly higher than the fix length FFT, it can implement the variable length FFT efficiently. Moreover, the proposed scheme can achieve a high throughput speed which satisfies the requirement of the real time orthogonal frequency division multiplexing (OFDM) signal processing for LTE system.

Orthogonal Frequency Division Multiplexing (OFDM) is one of the promising contendents in the race of very high data rate delivery, for 4G wireless systems. The conventional OFDM systems, so far deployed make use of Fast Fourier Transform (FFT) as their basic building block. Besides the numerous advantages, the restriction over the data rate imposed by the FFT in the form of cyclic prefix may be intolerable for the next generation OFDM systems. So, researches are on the way to replace FFT with a more suitable transform which is redundant free. DWT OFDM is one such system in which FFT in the conventional OFDM is replaced with Discrete Wavelet Transform (DWT). Using simulations, already it has been established that in ideal conditions, the performance of DWT OFDM is better than that of FFT OFDM. As phase noise can be considered as the major RF impairment and one of the leading performance limiting factors of the wireless systems, this paper analyses the Bit Error Rate (BER) performance of the DWT OFDM in presence of phase noise. BER performances of both DWT OFDM and FFT OFDM are analysed and compared in presence of phase noise. For this, Matlab Simulink model have been developed for both types of OFDM, and simulation is carried over in presence of phase noise for different modulation schemes. In all cases the BER performances of DWT OFDM is found to be fairly ahead that of FFT OFDM.

The computational complexity of FFT (Fast Fourier Transform) processing in an OFDM (Orthogonal Frequency Division Multiplex) based receiver is large with a large amount of receiver antennas. In LTE (Long Term Evolution) release 8, FFTs of different size are used for user data and random-access preambles [1] requiring additional FFTs to be implemented for random-access reception. Within the current paper, a 5G random-access preamble format is proposed based on a short sequence of the same length as the length of the OFDM symbols that are used for other uplink physical channels, such as user data, control signaling, and reference signals. The preamble sequence is constructed by repeating the short sequence multiple times. A corresponding preamble detector in which FFTs of the same size as for other uplink channels and signals are used is also described. In this way, the amount of special random-access related processing and hardware support is significantly reduced for multi-antenna systems with frequency-domain beamforming. This preamble detector is also robust against inter-carrier interference from other uplink channels and signals. Furthermore, the proposed preamble detector scheme can be used in 5G scenarios with a high amount of phase noise and frequency errors. For time-domain beamforming, the beamforming weights can be changed during preamble reception such that the number of spatial directions is increased for which preamble detection is done. Simulation results are used to compare preamble formats for different lengths of the sequences.

To reduce the processing time in Global Navigation Satellite System (GNSS) signal acquisition and tracking, we first propose a parallel method of signal acquisition and tracking as well as the associated software implementation in this paper. This paper applies the Message Passing Interface (MPI) and Open Multi-Processing (OpenMP) techniques for parallel computation implementation. This parallel method could put the multi-cores microprocessors to be efficiently used in GNSS signal acquisition and tracking processes. To further enhance the performance, this paper then proposes a new GNSS acquisition and tracking method, and it includes the multi-PRN code acquisition method we proposed in [Y. C. Lin and C. C. Sun, ION GNSS 2007] to reduce the acquisition processing time and a new FFT (Fast Fourier Transform)-based tracking method. This FFT-based tracking method combines the conventional tracking method and the FFT technique to track the incoming signal. Consequently, the tracking process is divided into two phases: detection and FFT-based phases. This proposed FFT-based tracking method can reduce the computational load as well. This new acquisition and tracking method will be combined with the above parallel method to gain the maximum improvement in GNSS signal acquisition and tracking. Finally, we use the real data collected by a software GNSS receiver to validate the proposed method. This paper will also conduct the comparison between the proposed method and the conventional GNSS acquisition and tracking method, and the comparison criterions are the computational load and the processing time. The experiment results of this paper show the effectiveness of this proposed approach for GNSS signal acquisition and tracking.

Objectives: For Orthogonal Frequency Division Multiplexing (OFDM), Fast Fourier Transform (FFT) processoris required. So, in this work, a variable point Pipelined FFT processor is designed by utilizing Verilog language. Further transmitter and receiver blocks are designed to form OFDM system. Methods: Speed enhancement is the key area which is been looked into this project work. Pipelined Architecture that is going to be implemented is RS2DF (Radix-2 Single path Delay Feedback). Standard FPGA Flow is adapted to implement this project i.e., right from specification to bit file generation. Simulations and Synthesis will be done using Questasim and Xilinx ISE. Verilog Simulations will be compared with in-built MATLAB FFT Core. MATLAB is used for reference and verification. Findings: This Project clarified the usage of FFT IP and OFDM in Xilinx ISE focusing on a specific family of FPGA. The execution of the proposed algorithm ought to perform superior to anything the base algorithm with the all-out basic way getting additionally advanced along these lines expanding the speed of activity. maximum operation frequency achieved was 236.189MHz but in base paper maximum operation frequency was 30Mhz. The systems utilized are Interna1 and externa1 Pipe1ining of modules and Distributed LUT based idea, the target of the above methods is to lessen the basic way deferral and increment the general speed of activity of structure, the disadvantage is the increments in area and output latency. Area is not of a much issue as present day days FPGAs has immense measure of assets. Output 1atency should be taken consideration with additional rationale at whatever point FFT is coordinated with other system modules. Application: The project depicts technique for streamlining timing basic ways of FFT to work at higher-speeds, to be utilized as a feature of LTE Protoca1 or any wire1ess protoco1 such as WLAN and LDACS. Keywords: Fast Fourier Transform (FFT), Hardware Description Language (HDL), Orthogonal Frequency Division Multiplexing (OFDM), Pipeline, Verilog

This paper focuses on theoretical analysis, computational test and optimization of High Performance Computing Cluster (HPCC). Also known as Data Analytics Supercomputer (DAS), HPCC is built on Intel Many Integrated Core (MIC) for High Performance Linpack (HPL) test. Initially, a platform is configured by 5 nodes with an Intel® Xeon Phi <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">™</sup> Coprocessor 31S1P per node to analyze power consumption as well as parallel level of Intel MIC accelerator. Compiling with Message Passing Interface (MPI) library and Math Kernel Library (MKL), the "Make" file is modified and debugged by adjusting parameters in hpccinf.txt. According to multiple Infiniband nodes evaluation, the libhpl library of Intel is employed and value of NB is set to be 960 for a single node with one MIC while debugging. Moreover, this paper optimized the algorithm on Double Precision General Matrix Multiplication (DGEMM) test and PTRANS to acquire efficient, precise and truncated working time duration. From HPL and Gridding Program experimental results, it's clear that the theoretical analysis and experiments were performed successfully.

Fast Fourier Transform (FFT)/Inverse Fast Fourier Transform (IFFT) are the key computation block in Orthogonal Frequency Division Multiplexing (OFDM) system. They dominate most of the areas and power dissipation in implementation therefore efficient low-power and high-throughput implementation of FFT processor is essential for successful deployment of OFDM based system. High-throughput and Low-power 128-point FFT Processor is designed using Radix-25 algorithm to reduce computation complexity and the feedforward pipeline architecture [called Multipath Delay Commutator (MDC)] with four data path for providing higher throughput. This architecture is more hardware-efficient than Multipath parallel feedback (MDF) design, which makes them attractive for the computation of FFT in most demanding applications. The proposed FFT processor uses improved Digit slice multiplier for complex multiplication. This proposed FFT processor is designed using Verilog and implemented using 180 nm CMOS Technology with supply voltage of 1.8v. The result shows significant reduction in power consumption in comparison with existing design and increasing throughput with area trade off.

Fast Fourier transformation (FFT), a kernel data processing task in communication systems, has been studied intensively for efficient software and hardware implementations. Nowadays, various orthogonal frequency division multiplexing (OFDM)-based wireless communication standards have raised more stringent requirements on both throughput and flexibility for FFT computation. Application-specific instruction set processor (ASIP) has emerged as a promising solution to meet these requirements. This paper presents a novel hierarchical design of an ASIP tailored for FFT. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array structure can easily expand along both the horizontal and vertical dimensions for any-point FFT computation. We incorporate custom register files to reduce memory access and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set architecture (ISA) with new instructions to accelerate FFT operations. An FFT ASIP is implemented on Tensilica's reconfigurable processor platform. Our FFT ASIP achieves the data throughput of 405.7 Mb/s for 1 K-point FFT, which attains UWB-OFDM specifications. The area of our custom processor is 147 kilo gates and the total processor power consumption is 60.7 mW, which are acceptable compared to several other designs such as application specific integrated circuit, digital signal processing, field-programmable gate array, and other ASIP implementations. We also extend the implementation for up to 8 K-point FFTs, with degraded performance but still meeting the requirements of those communications standards that demand large-size FFT computations.

— Performance of pilot-aided channel estimation techniques such as the Least Squares (LS) method depends on not only on the signal-to-noise ratio (SNR), channel conditions and pilot ratio, but also on the choice of interpolation method for deriving channel estimates at non-pilot subcarriers. This paper investigates the bit-error-rate (BER) performance of linear, spline and Piecewise Cubic Hermite Interpolating Polynomial (PCHIP) interpolation methods in LS channel estimation over the three extended ITU channel profiles defined for Long Term Evolution (LTE) testing. Simulation results show that applying the linear interpolation method produces the best BER performance over the fading channel with the smallest multipath delay spread. It is also shown that the choice of best interpolation method actually depends on the SNR in some of the fading channel profiles. Index Terms—ITU, LS, LTE, PCHIP, spline. I. INTRODUCTION Orthogonal frequency division multiplexing (OFDM) technology has been adopted in many of the next generation communication systems such as Long Term Evolution (LTE) and Worldwide Interoperability for Microwave Access (WiMAX) [1]. OFDM is preferred not only because it offers high data rate transmission but also because of its flexibility and robustness against multipath fading [1]. Multipath channel fading exists when multiple delayed copies of a transmitted signal are received at the receiver, thereby resulting in the distortion of the transmitted signal. These distortions are collectively termed „channel fading‟, causing reception errors and hence increased bit-error-rate (BER). Channel fading can be broadly classified as time-selective and/or frequency selective, depending on the relationship between the fading channel and the transmitted signal parameters [2]. To combat multipath fading and improve BER, some form of channel estimation method is required in order to estimate the channel distortion effect for each of the active subcarriers within an OFDM symbol [3].

Multi-input-multi-output (MIMO) systems along with orthogonal frequency division multiplexing (OFDM) technique plays a crucial role in 4G based wireless networks. The inclusion of MIMO technology enables new types of links such as downlink multi-user communication. Long term evolution (LTE) systems are based on multi-user MIMO technologies, which have flexible bandwidths. In this paper, we derived closed form expression of bit error rate (BER) for multi-user LTE and LTE-Advanced (LTE-A) systems. Moment generating function (MGF) and pair-wise error probability (PEP) based approaches are used to derive these BER expressions. Theoretical results of BER are validated using simulation results for different number of users. Results are plotted on the basis of various features such as coordinated multipoint (CoMP) transmission and reception, multimedia broadcast and multicast services (MBMS) and allocation of Bandwidth in LTE and LTE-A systems.

Long Term Evolution (LTE) is an access technique that is used in radio networks. LTE provides high data bandwidth in transmitting data by providing flexibility against noise and interference. Orthogonal Frequency Division Multiplexing (OFDM) technique uses the FDM (Frequency Division Multiplexer) modulation technique to increase the amount of carried information over the wireless network. The OFDM signal is transmitted to the receiver at different frequencies which they are orthogonal to each other by dividing the bandwidth of a signal into smaller sub-carriers. Recently, the use of polar codes as a coding scheme in the new generation 5G systems has come to the communications markets. Polar codes as a channel coding scheme are a promising technique for the future because it is the first codes that reach Shannon capacity limit. The cyclical prefix – OFDM (CP-OFDM), which is used in 4G systems, performs well in many aspects, however, it has much weakness that make the researches look for a new modulation technique to be used in 5G systems. Filtered–OFDM (F-OFDM) is considered one solution to the problems appeared in CP–OFDM. In this paper, the differences between CP-OFDM and F-OFDM regarding advantages and disadvantages of each type are studied in details. The comparison between the two modulations waveforms are done by studying their Error Vector Magnitude (EVM) that deals with measuring the accuracy of the received signals. Furthermore, the comparison between the two modulations waveforms with polar codes in the USRP B210 radio are applied to make our work more practical.

These days we find an enormous growth in wireless communication technologies. The use of OFDM in wireless systems has created a way to provide high data rates, less intercarrier interference(ICI), and less intersymbol interference(ISI). OFDM has become the core of most 4G communication systems, a Long Term Evolution (LTE) system. OFDM system divides the available signal spectrum into smaller bandwidths and transmits them to the receiver without interference with each other by inserting the cyclic prefix in between the signals. LTE uses OFDM for downlink, SC-FDMA for uplink and MIMO for enhanced throughput. The OFDM uses inverse fast fourier transform(IFFT) and fast fourier transform(FFT) for conversion of data. The system performance is measured by correlating the signal to noise ratio to bit error rate. The system performance is evaluated to study the effect of various LTE design parameters by simulating in MATLAB

We propose an method of implementing simultaneously despreading operation for high speed downlink packet access (HSDPA) wideband code division multiple access (W-CDMA) signals using fast Fourier transform (FFT). HSDPSA is a part of the W-CDMA standard and it provides an access method for high speed data communications. The basic idea of the HSDPA is similar to that of the orthogonal frequency division multiplex (OFDM), namely, instead of using multiple frequency to transmit symbols, HSPDA uses multiple spreading codes to transmit symbols. Although the idea is same, they uses different transformation for multiplexing: OFDM uses the fast Fourier transformation (FFT) and, on the other hand, HSDPA (WCDMA) uses Walsh-Hadamard transformation (WHT). Therefore, it becomes hard to implement these two technologies into a single configuration. The proposed method implement the despreading process as a combination of an FFT and a post-processing. By computer simulation, it is shown that the proposed method provides same BER performance with that of the direct despreading calculation. Moreover, we show that, by generalizing the configuration of the proposed method, WCDMA can be expressed as a special case of the multicoded multicarrier (MC-MC) CDMA. MC-MC CDMA is a newly proposed multiplexing method and is a mixture of the OFDM and CDMA technologies. We show that all of OFDM, MC-MC CDMA and WCDMA can be implemented by a combination of an FFT and a multiplication of orthogonal matrix. Hence, using the proposed method, we can implement those three technologies into a single configuration.

Intel's Many-Integrated-Core (MIC) architecture aims to provide Teraflop throughput (through high degrees of parallelism) with a high FLOP/Watt ratio and x86 compatibility. However, this two-fold approach to solving power and programmability challenges for Exascale computing is constrained by certain architectural idiosyncrasies. MIC coprocessors have a memory constrained environment and its processors operate at slower clock rates. Also, being PCI devices, the communication characteristics of MIC co-processors are different compared to communication behavior seen in homogeneous environments. For instance, the performance of sending data from the MIC memory to a remote node's memory through message passing routines has 3x-6x higher latency than sending from the host processor memory. Hence communication libraries that do not consider these architectural subtleties are likely to nullify performance benefits or even cause degradation in applications that intend to use MICs and rely heavily on communication routines. The performance of Message Passing Interface (MPI) operations, especially dense collective operations like All-to-all and All gather, strongly affect the performance of many distributed parallel applications. In this paper, we revisit state-of-the-art algorithms commonly used to implement All-to-all collectives and propose adaptations and optimizations to alleviate architectural bottlenecks on MIC clusters. We also propose a few novel designs to improve the communication latency of these operations. Through micro-benchmarks and applications, we substantiate the benefits of incorporating the proposed adaptations to the All-to-All collective operations. At the micro-benchmark level, the proposed designs show as much as 79% improvement for All gather operation and up to 70% improvement for All-to-all and with the P3DFFT application, an improvement of 38% is seen in overall execution time.