Two language levels for system programming

The PDOP (Position Dilution of Precision) is a key index used for evaluating the effect of satellite-receiver geometry on the accuracy of positional parameters. In multi-GNSS positioning, the time offsets between different systems can be calculated at system level or user level. The two methods have different ways to deal with the time offsets, but they have the same positional parameters about the receiver position. We focus on the characteristics of the PDOP related with the accuracy of the positional parameters in this work. The comparison of the sizes of the PDOP at system level and user level has been derived and it can enrich the research in multi-GNSS positioning. Moreover, the basic reason why the PDOP has this property has also been discussed.

The level of support for high level programming languages (HLPLs), despite the claim of support by some of the newly introduced microprocessors, is inadequate despite the falling (rising) cost of hardware (software). Computer systems that are to be used to run programs written exclusively in HLPLs have a need for a multiprocessor/multiarchitecture microprocessor design (M3D); the personal/desk-top computers are prime examples. The HLPLs that will be used in programming these systems will be grouped according to their structures. Each group of languages will require their own instruction set; the hardware and software needs will determine the type of architecture configuration, i.e. aspects such as: register-to-register, memory-to-memory, stack, or a combination of these. The overall system should be divided up into functional units, e.g. ALU, compiler/translator, etc. Each functional or subfunctional unit will be implemented in software, firmware, hardware, or a combination of these with implementation decision based on the speed criticality, cost, technology, and the need to modify the unit. This approach will lead to a cop-down-design, and will also reduce the semantic gap, software and system cost, and down-time.

Background/Objectives: To meet the challenge of increasing design complexity, designers are turning to System Level Design Languages (SLDLs) to model systems at a higher level of abstraction. Methods/Statistical Analysis: Now there are some system level languages like SystemC but hardware developers prefer HDL based languages like VHDL for coding. So focusing on methods for extending VHDL for system-level modeling is the issue of hardware modeling researches. VHDL itself has some high level structures to model near system-level. Here we have implemented a 9 switch Network-on-Chip (NoC) with processing and communication elements like FIFOs and we have tried to eliminate signals as communication elements between processing components and using high level structures in addition to resolution function (for the first time in NoC structure) in routing algorithm. Finding: Resolution function can decrease simulation speed as in the literature mentioned so we have applied some improving techniques for simulation accelerating to see the result of these tradeoffs. All in all the one with resolution function and other high level structures besides applying improving speed rules has better performance and we have gain about 28% speed up and 35% speed up in contrast to the latter one without eliminating possible signals. Conclusion/Application: All in all by using accelerating rules we had no simulation time penalty and gained 28% speed up. Resolution function is a high level structure which is used for hardware purposes, it is preferable than simply implementing the routing algorithm by other common statements.

Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of systems on a chip (SoCs). We propose a technique to alleviate the complexity of the equivalence checking problem, by efficiently decomposing it using compare points. Traditionally, equivalence checking techniques use nominal or functional mapping of latches as compare points. Since we operate at a level where design descriptions are in system level languages or hardware description languages, we leverage the information available to us at this level in deducing sequential compare points. Sequential compare points encapsulate the sequential behavior of designs and are obtained by statically analyzing the design descriptions. We decompose the design using sequential compare points and represent the design behavior at these compare points by symbolic expressions. We use a SAT solver to check the equivalence of the symbolic expressions. In order to demonstrate our technique, we present results on a non-trivial case study. We show an equivalence check between a SystemC description and two different Verilog RTL implementations of a Viterbi decoder, that is a component of the DRM SoC.

Welcome to the DATE 08 Conference Proceedings. DATE combines the world's favourite electronic systems design conference and Europe's leading international exhibition for electronic design, automation and test, from system level hardware and software implementation right down to integrated circuit design. The DATE 08 event features a technical program with 77 sessions covering the latest developments in system design and embedded software, IC design/test methodologies and EDA tools, together with an exhibition with the leading EDA, silicon and IP providers showing their new products and services. Challenges that you all face or soon will face in your daily practice are the increasing design complexity of highly integrated systems, the introduction of reconfigurability and embedded software, and the control of power and variability in nanometer IC designs. All these issues will be addressed in this year's DATE event. For the 11th successive year DATE has prepared an exciting technical programme, with the help of the more than 400 members of the Technical Programme Committee, who dedicated their time to thoroughly review the 839 submissions in 37 topics, ranging from system level down to circuit design and covering all the most relevant application domains. The submissions are organised in 4 major areas: D --- Design Methods, Tools, Algorithms and Languages A --- Application Design T --- Test Methods, Tools and Innovative Experiences E --- Embedded Software After a thorough review and selection process (with an average of 5 reviews per paper), finally 198 regular papers were selected for presentation at the conference. Additionally, there are 46 Interactive Presentations that are organised in 5 IP sessions. Together with the invited special sessions (panels, embedded tutorials and hot topic sessions), this has resulted in a high-quality technical program. The technical program provides a wide but high-quality coverage of design, design automation and test topics, from the system level to the integrated circuit level. Compared with previous years, submissions in the Embedded Software track has increased by 50%, showing a clear trend towards a comprehensive system design focus with integrated hardware and software solutions. DATE has established itself firmly as a true Electronic System Design Conference. This year the conference is held in Germany, at the ICM in Munich and spans an entire working week from Monday March 10 to Friday March 14. On Monday, eleven pre-conference tutorials will be given. The three-full day tutorials cover topics of great interest for system design. The first tutorial deals with techniques to automatically realising embedded system from high-level functional models. The second tutorial addresses the different issues related to communication based design and architectures in automotive electronic systems. The third tutorial discusses several key concepts on system-level design and application mapping for wireless and multimedia MPSoC architectures. Furthermore, eight half-day tutorials are also given, which cover a wide spectrum of topics on specification, modelling, design and test. The main conference opens on Tuesday March 11, with two very interesting and complementary keynote speeches. Dominique Vernay, Chief Technical Officer for Thales, will talk about the challenges of embedded systems design, and Giovanni de Micheli, Professor at EPFL, will present his views on designing micro/nano systems for a safer and healthier tomorrow. On the same day, the Executive Track offers a series of business panels with executives discussing hot topics in design: the perils of 45 nanometers, the changes in EDA strategies from IDM, to fablite to fabless, and embedded systems level design strategies. DATE 08 will again offer two specific days related to special themes. On Wednesday March 12, a special full-day track is devoted to Automotive Electronics---Software and Architecture. This special-day track will focus on the challenges faced by the automotive supply chain with particular attention to system and software architecture design. It provides a comprehensive analysis of the evolution of automotive architectures, including ECUs, sensors and communication standards and discusses how new methods, tools and standards for interoperability and component-based design can deal with the increasing complexity of software systems and their need for reliability and guaranteed timely behaviour. In addition, it addresses to what degree existing standards, including AUTOSAR and FLEXRAY and model-based development, can support the development of safety and time-critical software. On Thursday March 13, a second special full-day track focuses on Dependable Embedded Systems. This track will address both conceptual and applied issues for design, analysis and validation of dependable embedded systems. The utility of embedded systems and services is based, in large part, on our depending on their sustained functionality in spite of the encountered operational or malicious disruptions. As the number of transient and also permanent disruptions (given the decreasing device geometries, higher device density, lower voltage latching, faster clocks etc) is expected to increase substantially, this will not only be a key issue for the hardware community but also the systems community in general. Solutions using a combination of hardware and software might be more effective than hardware-only or software-only solutions. This track focuses on both conceptual and applied issues for design, analysis and validation of dependable embedded systems. Besides these special tracks, the main conference is organized in six parallel tracks of sessions, three devoted to design methods, tools, algorithms and languages, one to application design, one to test methods, tools and innovative experiences, and finally one to embedded software. The presentations of the selected regular papers in these parallel tracks are complemented by nine Special Sessions and two Invited Industrial Sessions. The special sessions are organized in the form of panels, hot topics, and embedded tutorials. The topics to be covered include quantitative evaluation for embedded systems design, design and manufacturing at 32 and 22nm, software for wireless networked embedded systems, test challenges for low power devices, quantitative productivity measurement in IC design, and 3D Integration. The two invited industrial sessions deal with industrial system designs in transportation and information technologies. To emphasise that DATE is the major event for the designers, DATE 08 features also invited sessions where Europe's famous consumer industry presents their best designs and design practices. Friday March 14 is the day for the DATE workshops. DATE 08 offers workshops on current and emerging important issues in design, test, EDA and software to complement the regular conference. They provide a unique opportunity for the various research and design communities to spend a day discussing the latest and the best, sharing their experiences and visions. This year's workshop program includes eight workshop themes. Four workshops are related to software engineering, ranging from dependable software to modelling, analysis and development tools. Four other workshop themes cover a variety of topics such as the impact of process variations on design and test, the merging world of Nano-Electro-Mechanical Systems, new directions in high level synthesis, and heterogeneous reconfigurable hardware. Each workshop features presentations, invited or submitted, from highly distinguished academic and industrial researchers. Finally, throughout the conference days, DATE offers a comprehensive overview of commercial design and verification tools in its large exhibition hall. Exhibitors include EDA vendors, silicon, FPGA and IP providers showing their new products and services. In addition, there is an Exhibition Theatre featuring talks from engineering managers of the leading electronic manufacturers on first-hand design experiences of commercial EDA tools. New this year is the European projects village where different European and large government funded projects will be able to show their ongoing research and results to the design community and have the opportunity for internal meetings and discussions. The DATE week will be also an opportunity for students and universities to show their research work, through the PhD Forum on Monday evening and the University Booth where hardware and software demonstrations will be shown by different universities on a rotation schedule. The DATE 08 event's program will be particularly attractive to industrial designers, at analog, IC, FPGA and embedded system level, as well as software designers, to researchers and academics as well as to design managers, and an increasing attendance is expected. We therefore invite you to take full advantage of the many opportunities offered to you by DATE 08, to extend your knowledge and/or business in electronic system's design and to exploit the abundant networking possibilities offered to socialise with colleagues, including fringe meetings and a memorable social party with bands and dancing. We hope that you will all enjoy the DATE 08 Conference and Exhibition.

The paper deals with problems of high level modeling of real-time systems in system level languages. Main advantages of transaction level modeling in SystemC are emphasized. The universal kernel for functionality, communication and timing issues modeling is presented. The problem of multithreading is exemplified on sorting procedure implemented in multi-core microprocessor system. Advantages of system level approach to modeling and design of real-time systems are outlined.

Research has suggested that the activity occurring in a variety of social, economic, and technological systems exhibits long-range fluctuations in time. Pronounced levels of rapidly occurring events are typically observed over short periods of time, followed by long periods of inactivity. Relatively few studies, however, have shed light on the degree to which inhomogeneous temporal processes can be detected at, and emerge from, different levels of analysis. Here we investigate patterns of human activity within an online forum in which communication can be assessed at three intertwined levels: the micro level of the individual users; the meso level of discussion groups and continuous sessions; and the macro level of the whole system. To uncover the relation between different levels, we conduct a number of numerical simulations of a zero-crossing model in which users' behavior is constrained by progressively richer and more realistic rules of social interaction. Results indicate that, when users are solipsistic, their bursty behavior is not sufficient for generating heavy-tailed interevent time distributions at a higher level. However, when users are socially interdependent, the power spectra and interevent time distributions of the simulated and real forums are remarkably similar at all levels of analysis. Social interaction is responsible for the aggregation of multiple bursty activities at the micro level into an emergent bursty activity pattern at a higher level. We discuss the implications of the findings for an emergentist account of burstiness in complex systems.

This article discusses strategies for integrating knowledge-based systems techniques with conventional computer science techniques. The effect of such an approach has led to the production of an intelligent systems development environment called INDEX. INDEX supports a layered architecture to enable expert system functionality to be generated and integrated at language level, tool level, and system level within a traditional software environment. At the language level, INDEX provides a set of expert system primitives describing low-level operations of an expert system. These primitives can be accessed from most of the conventional languages. At tool level, expert system primitives and relevant INDEX facilities are used in producing expert system tools and various mediation tools for tool integration. At the system level, INDEX can be used to build integrated/coordinated systems. Several applications have been given to demonstrate the effectiveness of our approach, and its future directions. © 1996 John Wiley & Sons, Inc.

The paper describes the design of a genetic classifier-based intrusion detection system, which can provide active detection and automated responses during intrusions. It is designed to be a sense and response system that can monitor various activities on the network (i.e. looks for changes such as malfunctions, faults, abnormalities, misuse, deviations, intrusions, etc.). In particular, it simultaneously monitors networked computer’s activities at different levels (such as user level, system level, process level and packet level) and use a genetic classifier system in order to determine a specific action in case of any security violation. The objective is to find correlation among the deviated values (from normal) of monitored parameters to determine the type of intrusion and to generate an action accordingly. We performed some experiments to evolve set of decision rules based on the significance of monitored parameters in Unix environment, and tested for validation.KeywordsGenetic AlgorithmIntrusion DetectionClassifier SystemIntrusion Detection SystemMonitor ParameterThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

<p>The use of Business Intelligence for Small-Mid Enterprise (SME) no longer impeded by the size of the resources required. The study in this paper provides an overview of how the use of proposed software can be used as an effective and efficient alternative solution in building BI Tools combined with table virtualization utilization in SQL. To know the level of usability and suitability of the developed BI Tool, the researcher conducted evaluation and analyzation using 2 (two) tools (Heuristics Evaluation and UMUX-Lite). The result found the comparison between the output (Business Intelligence Tool) produced by PHP Report Maker has a better level of usability and suitability than its competitors. Although both are in a decent median, the output needs preferences and customizations to achieve maximum functionality like well-known other development software. </p>

This article describes an approach to identification and certification in a decentralized environment. The protocol defines the way to integrate blockchain technology and web-of-trust concepts to create a decentralized public key infrastructure with easy user ID management. The essence of the scheme is to differentiate the entire infrastructure into 2 levels: the level of certification authorities (service providers) that jointly keep track of events related to user certificates; and the level of end users, systems and applications. During creating, updating, and revoking certificates, higher-level members reach a consensus on the confirmation of transactions associated with them, which ensures a higher level of validity of the certificates and synchronization of their status between certification centers. In turn, lower-level members do not need to perform complex verification procedures for a corresponding certificate: unlike the classic X.509 architecture and web-of-trust approach, the maximum number of checks in a chain can be two. An important feature of such a system is its ability to refuse certification centers: in the case of failure and / or compromise of the keys of one certification center, other network members continue to work seamlessly with others, and blockchain technology may make it impossible to add a certificate to a center whose keys have been compromised, because all the events in the system are connected by cryptographic methods. In particular, such a system can be used on the Internet of Things. Each individual sensor must communicate properly with other components of the system as a whole. In order to enable the secure interaction of these components, they must exchange encrypted messages to verify their integrity and authenticity, the provisioning scheme of which is in the described scheme.

This paper describes the achievements and benefits obtained using an electronic-based Brake Control unit, METROFLEXX, suitable to perform Emergency and Service brake function with the high Safety Integrity Level (SIL). METROFLEXX replaces the complete traditional electro-pneumatic brake system, by performing a real time emulation of functions that are traditionally performed by pneumatic components. Therefore, METROFLEXX has been developed comply with the following CENELEC safety standards that represent the state-of-art for the railway transit market at European and worldwide level: EN 50126 (system level), EN 50129 (electronics hardware), EN 50128 (software), EN 50159 (safety related communication). An Independent Safety Assessment (ISA) has been completed by receiving the assessment report and the corresponding attestation of conformity from a recognized ISA company. Thanks to the METROFLEXX, several benefits can be achieved at system and train level, such as improved service reliability, improved safety and a better Total Cost of Ownership (TCO).

Reflection and automated introspection of a design in system level design frameworks are seen as necessities for the CAD tools to manipulate the designs within the tools. These features are also useful for debuggers, class and object browsers, design analyzers, composition validation, type checking, compatibility checking, etc. However, the central question is whether such features should be integrated into the language, or if we should build frameworks which feature these capabilities in a meta-layer, leaving the system-level language intact. In our recent interactions with designers, we have found differing opinions. Especially in the context of SystemC, the temptation to integrate reflective APIs into the language is great, because C++ is expressive, and already has type introspective packages available. In this paper, we analyze this issue and show that (i) it is a better EDA system architecture to implement reflection/introspection at a meta-layer in a design framework (ii) there are relatively unexplored territories of design automation, such as behavioral typing of component interfaces, corresponding type-theory, and their implication in automating component composition, interface synthesis, and validation, which can be better incorporated if the introspection is implemented at a meta-layer.

Variants of general-purpose programming languages, like SystemC, are increasingly used to specify system designs that have both hardware and software parts. The system-level languages allow a flexible partitioning in the design of the hardware and software. Moreover, many properties depend on the combination of hardware and software and cannot be verified on either part alone. Existing tools either apply non-formal approaches or handle only the low-level parts of the language. This papers presents a new technique that handles both hardware and software parts of a system description. This is done by automatically partitioning the uniform system description into synchronous (hardware) and asynchronous (software) parts. This technique has been implemented and applied to system level descriptions of several industrial examples. The hardware/software partitioning improves the performance of the verification compared to the monolithic approach.

the University of Amsterdam, May 20-31, 1974.This Tract collects the lecture notes of five of the courses given.The sixth course, given by Dr. R. Kowalski on Predicate Logic as a Programming Language in Artificial Intelligence, is scheduled to appear elsewhere.We are very grateful to the Netherlands Organization for the Advancement of Pure Research (Z.W.O.)