Type Systems for Distributed Programs: Components and Sessions

Reconfiguration technique has been considered as one of the most promising electronic design automation (EDA) technologies in MPSoC design paradigms. However, due to the unavoidable latency in the reconfiguration procedure, it still poses a significant challenge to efficiently analyze the trade-offs for the software/hardware execution, static reconfiguration and dynamic reconfiguration. In this paper we first present a heterogeneous MPSoC middleware to support state-of-the-art dynamic partial reconfigurable technologies. Furthermore, we evaluate the reconfiguration latency and analyze the trade-off for the dynamic partial reconfiguration technologies.

Functional programs are well suited for concurrent execution due to the Church-Rosser property. However, for many applications there is still need to explicitly specify process systems instead of relying on compilers. Coordination languages provide one viable solution to the problem of specifying concurrent process systems, since they do not interfere with the properties of the language used for the algorithmic specification of the processes. The coordination language K2 to be proposed in this paper is based on a variant of colored Petri nets. It primarily defines process systems with deterministic behavior, but also allows for controlled forms of non-determinism. Specifications based on Petri nets offer several advantages. An underlying net calculus facilitates formal analysis and verification of basic safety and liveness properties. Graphical representations clearly expose structural dependencies among system components. Our variant of colored Petri nets provides several forms of net abstractions which facilitate the systematic construction of complex systems from small subsystems by composition. Recursive specifications can be used to adapt the structure of a process system to actual problem sizes or to varying input parameters.KeywordsInput StreamOutput StreamLiveness PropertyRecursive ProcessHierarchical ProcessThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

The major problem in an interconnection network is related with the contention due to message blocking. In order to avoid this problem, many alternatives have been proposed in the literature, mainly adaptive routing, random routing and dynamic network reconfiguration. Our paper deals with dynamic reconfigurable networks. Reconfigurable networks are an alternative to reduce the negative effect that congestion produces on the performance of the network. Network reconfiguration can be done in different ways. Our researches are focused on dynamic reconfiguration. This technique consists basically of placing the different processors in the network in those positions which, at each computational moment and according to the existing communication pattern among them, are more adequate for the development of such computation.

Embedded devices are equipped with specialized microcontrollers for each device. If an ultra-general purpose microcontroller with all peripherals existing, any kind of embedded device can be developed by such microcontroller. However, such microcontrollers cannot be built due to the scale and price. A dynamic partial reconfigurable microcontroller (DPR microcontroller), which has a function to switch circuits for each application, can realize an ultra-general purpose microcontroller that can be used for any application. For the realization and practical use of DPR microcontrollers, it is necessary to develop a hardware library-like structure in which optimized interface circuits for each peripheral device are designed in advance. In addition, the impact of dynamic switching of peripheral device interface circuits on performance has not been studied, so it is necessary to evaluate these effects. Using dynamic partial reconfiguration, we measure the execution time, circuit size of the entire system, and power performance improvement ratio of a single system that displays a binarized image on an LCD module after gray scaling and binarizing the image. The results show that the dynamic partial reconfiguration can be used to improve the performance of the system. As a result, we confirmed that the system works correctly even when dynamic partial reconfiguration is used. In addition, we were able to improve the processing speed by about 2.13 times compared with software processing, and reduce the circuit size by about 24%. We also achieved a 13.8-fold improvement in power consumption.

Service-oriented architecture provides the ability to combine several web services in order to fulfil a user-specific requirement. In dynamic environments, the appearance of several unforeseen events can destabilize the composite web service (CWS) and affect its quality. To deal with these issues, the composite web service must be dynamically reconfigured. Dynamic reconfiguration may be enhanced by avoiding the invocation of degraded web services by predicting QoS for the candidate web service. In this paper, we propose a dynamic reconfiguration method based on HMM (Hidden Markov Model) states to predict the imminent degradation in QoS and prevent the invocation of partner web services with degraded QoS values. PSO (Particle Swarm Optimization) and SFLA (Shuffled Frog Leaping Algorithm) are used to improve the prediction efficiency of HMM. Through extensive experiments on a real-world dataset, WS-Dream, the results demonstrate that the proposed approach can achieve better prediction accuracy. Moreover, we carried out a case study where we revealed that the proposed approach outperforms several state-of-the-art methods in terms of execution time.

In high performance computing (HPC), applications usually have many parallel tasks running on multiple machine nodes. As these tasks intensively communicate with each other, the communication overhead has a significant impact on an application's execution time. This overhead is determined by the application's communication pattern as well as the network distances between communicating tasks. By mapping the tasks to the available machine nodes in a communication-aware manner, the network distances and the execution times can be significantly reduced.

Deep potential (DP) scheme has increased the simulation temporal and spatial scales while maintaining the ab initio accuracy of the molecular dynamics. DeePMD-kit is an outstanding application that implements DP scheme efficiently. However, current performance model cannot accurately measure the resource utilization of DeePMD-kit operators and predict the execution time. We introduce DP-perf, an interpretable performance model for DeePMD-kit. DP-perf can accurately measure the resource utilization of the individual DeePMD-kit operators, communication pattern, and the overall application by exploiting physical system properties and machine configurations. It can be easily applied to mainstream supercomputers including Tianhe-3F, the new Sunway, Fugaku, and Summit. With DP-perf, users can select the optimal machine and decide the corresponding configuration for various purposes (e.g., lower cost, less time) without real runs. Evaluation of four top supercomputers shows that DP-perf can fit overall execution time with a low mean absolute percentage error of 5.7 %/8.1%/14.3%/13.1% on Tianhe-3F/new Sunway/Fugaku/Summit. On the prediction scenario, DP-perf can predict the total execution time with a mean absolute percentage error of less than 20%.

A microservice-based application is composed of multiple self-contained components called microservices, and controlling inter-service communication is important for enforcing safety properties. Presently, inter-service communication is configured using microservice deployment tools. However, such tools only support a limited class of single-hop policies, which can be overly permissive because they ignore the rich service tree structure of microservice calls. Policies that can express the service tree structure can offer development and security teams more fine-grained control over communication patterns. To this end, we design an expressive policy language to specify service tree structures, and we develop a visibly pushdown automata-based dynamic enforcement mechanism to enforce service tree policies. Our technique is non-invasive: it does not require any changes to service implementations, and does not require access to microservice code. To realize our method, we build a runtime monitor on top of a service mesh, an emerging network infrastructure layer that can control inter-service communication during deployment. In particular, we employ the programmable network traffic filtering capabilities of Istio, a popular service mesh implementation, to implement an online and distributed monitor. Our experiments show that our monitor can enforce rich safety properties while adding minimal latency overhead on the order of milliseconds.

In this paper, we propose a Multiple Core architecture and an DMA bus connectivity to increase the processing speed of encryption and authentication cores in high speed IPSec security systems. Dynamic partial reconfiguration technology (DPR) is used to reduce FPGA resources and power consumption on chips. This paper proposes a model for high-speed Multiple-IPSec security systems that meet real-time applications. The system throughput, power consumption, and resources used when applying Multiple-Core and DPR architectures are also calculated.

Chapter 11 - Load Balancing and Optimization

One of the primary objectives of ambient systems is to provide services based on the ability to interact with the environment (including objects, humans and system components). An ambient system must deal with the dynamic integration of new and unexpected elements (e.g. users or devices). To fulfil the system functions, we need to specify the ambient system and its dynamic context. In this paper, we present an elaborated formal approach to model the core concepts of context-aware systems and their dynamic reconfigurations. The approach enables a high-level of abstraction and supports building context-aware systems by providing modularity and separation of concerns. For this purpose, one, we use Milner’s standard bigraphs to model the contextual part of the context-aware system and second, we provide an extension of the Bigraphical Reactive System (BRS) to model the functional part of multi-agent system architectures (BRS-MAS). Finally, to evaluate the proposed approach, we use a Bigraphical Model Checker (BigMC) to verify safety and liveliness properties through a smart car management system case study.

: The goal of this effort Composability, Provability, Reusability (CPR) for Survivability is to address the problem of composition of survivable systems. The particular objective of this project is to construct a formal specification of the Java Virtual Machine (JVM) bytecode loader and verifier, and from that specification formally derive a provably-correct implementation. The specification and program development is being carried out using Kestral's Specware System. The security of Java applications depend on type safety and related properties enforced by bytecode verification. Serious Java security flaws have been traced to errors in Sun's Java bytecode verifier and loader. A formal specification will serve as a reference document for the construction of new JVM implementations for just-in-time compilers, web browsers, smart cards, etc. The desired safety and security properties of the verifier will be proved as putative properties of the formal specification. The formally-derived implementation can be used as a test oracle to test implementations, or may be incorporated directly into a JVM implementation.

In recent years, system of systems resilience has been widely studied. System of systems has obvious resilience properties when considering dynamic reconfiguration in the following four parts: avoidance, survival, adaption and recovery. System of systems can be downgraded and recovered by reconfiguring resources to keep the performance output enough to satisfy the threshold under internal failure or external shocks. In other words, because of dynamic reconfiguration, system of systems has obvious characteristics of resilience. In this study, first, a new resilience model for systems and system of systems based on the performance threshold is proposed. Second, military system of systems is decomposed hierarchically, including system of systems–level, platform-level and system-level top-down, respectively. Third, a radar network of military system of systems is taken as a typical case. A performance model for a radar network under internal or external shocks is established based on the linear-Gauss-Poisson process in system of systems, and its parameters are discussed in detail. Finally, a typical 5-node radar network of formation air defense military system of systems is taken as an example to demonstrate proposed models and methods. The reliability and resilience loss are achieved by considering internal failure or external shocks, which can serve as a reference for evaluating and improving the effectiveness of system of systems.

Current trends in HPC (high performance computing) suggest that clusters will soon consist with hundreds, if not thousands, processors and the size of current scientific problems becomes much larger than before. Many researchers have predicted that the communication among these processors has dominated the execution time of the scientific parallel applications. Users will need well understanding on communication patterns among scientific parallel applications and their similarities so that users benefit not only from cost saving on constructing the running environment for these applications but also from obtaining better performance. In this paper, we address the communication pattern matching, and focus on point-to-point communication, which is primarily utilized (over 90% all MPI (message passing interface) calls) in most MPI codes and has much more impact on the communication performance than collective communication does. In this work, our contribution is that we propose a new approach MPACP (matching of parallel application communication patterns) to automate the analysis of the similarity between two parallel applications and provide a reliable report which will help users or developers understand the similarity among communication patterns of parallel applications. Furthermore, experimental results demonstrate the effective performance of our scheme in terms of the automatic matching of parallel application communication patterns.

The direct method for solving N-body problems maps perfectly onto hypercube architectures. Unlike other hypercube implementations, we have implemented a direct N-body solver on the Connection Machine CM-2 which makes optimum use of the full bandwidth of the hypercube. When N > P, where P is the number of floating-point processors, the communication time of the algorithm is negligible, and the execution time is that of the arithmetic time giving a P-fold speed-up for real problems. To obtain this performance, we use “rotated and translated Gray codes” which result in time-wise edge disjoint Hamiltonian paths on the hypercube. We further propose that this communication pattern has unexplored potential for other types of algorithms. Timings are presented for a collection of interacting point vortices in two dimensions. The computation of the velocities of 14,000 vortices in 32-bit precision takes 2 seconds on a 16K CM-2.