Ultra-low-power and compact 8-bit CMOS priority encoder

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison.

The FinFET based Full Adder in various cell designs is investigated in terms of performance and energy efficiency. Additionally, the performance of the FinFET Full Adder in the subthreshold region reveals significant results in low power technology. The 1-bit FinFET based Full Adder is designed in four different cell designs, and while the average power dissipated, delays, power-delay-product (PDP) and energy-delay-product (EDP) of all four topologies were analyzed based on the types of transistors used i.e. conventional Field Oxide Transistor (MOSFET) and FinFET. Based on this study, FinFET based Full Adder shows an average of 94 % reduction in delay, 97 % reduction in power dissipation and 99 % reduction for both PDP and EDP over the conventional FET, giving FinFET advantages in energy efficiency.

GDI (Gate Diffusion Input) - a new technique of low power digital circuit design is described. This technique allows reducing power consumption, delay and area of digital circuits, while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various PTL design techniques is presented, with respect to the layout area, number of devices, delay and power dissipation, showing advantages and drawbacks of GDI as compared to other methods. A variety of logic gates have been implemented in 0.35 /spl mu/m technology to compare the GDI technique with CMOS and PTL. A prototype test chip of 8-bit CLA adder has been fabricated, based on GDI and CMOS cell libraries, showing up to 45% reduction in power-delay product in GDI. Properties of implemented circuits are discussed, simulation results are reported and measurements of a test chip are presented.

This paper deals with low power multiplier design that plays a significant role in green wireless communications systems. Over the period of time, researchers have proposed various multiplier designs in order to get high speed. Vedic multiplier is considered as one of the low power multiplier along with high speed as compared with traditional array and booth multipliers. Vedic Multiplier contains a total of sixteen algorithms/sutras for predominantly logical operations. This research focuses on thermal aspects and energy efficiency of wireless communications systems with the thermal aware low power design of Vedic Multiplier. Temperature plays an important role on the performance of any device. The primary purpose of this research is to enhance the thermal stability of the wireless communications. Energy efficient IO standards are used to decrease the power dissipation of Vedic Multiplier and that eventually decrease power dissipation of wireless communications systems. In order to study the effect of different process technology (40, 65, 90 nm) on our design, a novel design is implemented on 40, 65 and 90 nm based FPGA. In this work, we are integrating thermal aware design approach for energy efficient Vedic Multiplier on various FPGA using LVCMOS and HSTL I/O standard. LVCMOS is an acronym for Low Voltage Complementary Metal Oxide Semiconductor and HSTL is an acronym for High Speed Transceiver Logic. In this Vedic Multiplier, we are using three LVCMOS I/O standard and nine HSTL I/O standard. In order to test the thermal sustainability of our Vedic Multiplier design, we are testing it in three different room temperatures i.e. 20, 30, and 40 °C. Using LVCMOS25, there is 12.99, 19.23 and 10.28% reduction in power dissipation on 90, 65 and 40 nm FPGAs respectively. For LVCMOS25, when our Vedic Multiplier design is migrated from 40 nm design to 90 nm FPGA design, there is 87.72% reduction in power dissipation of Vedic Multiplier when temperature is kept constant at 20 °C. When temperature is scaled down from 50 to 20 °C there is 12.45, 14.93, 12.84, 9.45 and 8.48% saving in power dissipation on using HSTL_I, HSTL_I_12, HSTL_I_18, HSTL_I_DCI and HSTL_I_DCI_18 IO Standard respectively on 90 nm FPGA.

Most of the VLSI applications, such as DSP, image and video processing, and microprocessors use carry select adder (CSLA) for arithmetic functions. From the structure of regular SQRT CSLA, still there is possibility to obtain better design in which optimization of area, power are to be major concentrations along with high speed performance. One of the existing solutions used in SQRT CSLA is replacement of second level RCA by BEC. Though increases the performance, very less percentage of improvement in reduction of area and power dissipation. And also the existing adder with BEC technique is not suitable for low power applications. Hence this paper proposes Special Hardware using Multiplexers (SHM) design in place of second level RCA. It is observed from the results that the area and power dissipation are reduced at comparable percentages with respect to the RCA and BEC techniques. When SHM is used at the second level of second block in 16-bit SQRT CSLA, observed that area is reduced by 13.5% and power dissipation is reduced by 6.4%. This proposed logic is designed in transistor level using 0.12µm technology in the Micro wind tool.

This research presents a novel single-architecture universal shift register/counter with an integrated memory unit. A full swing gate diffusion input (GDI) flip-flop is designed and implemented in both a synchronous counter and a universal shift register. SRAMs are mostly utilized as cache memory due to their ability to retain data when the power is ON. Hence, a 4 × 4 SRAM-based on full swing gate diffusion input flip-flop is developed to act as a memory for the proposed single-architecture universal shift register / Counter with the memory unit. To enhance performance, a 4 × 4 SRAM based on the proposed GDI flip-flop is incorporated as the memory unit. The design aims to improve key performance metrics, including clock-to-Q delay, power-delay product, area, and static power consumption. Simulation results demonstrate a 25% reduction in clock-to-Q delay, 30% reduction in D-to-Q delay, 20.2% reduction in power-delay product, 14.9% reduction in area, and 28.6% reduction in static power consumption compared to conventional D-flip-flop designs. The proposed architecture is validated through simulations using Tanner EDA at 1.2 V operating conditions, confirming its efficiency and potential applicability in high-performance sequential circuits.

This work targets characterization of the architectural power implications of precision limited arithmetic operations during floating point FIR filtering. Instrumented digital filter programs that emulate a DSP multiply-accumulate unit form the core of our experimental platform. The experiments substantiate the validity of our transition activity scaling based approach for the design of low power floating point adders and multiply accumulators (MACs). With precision limited low pass filtering, the worst case power reduction offered by the proposed transition activity scaled triple data path floating point adder (TDPFADD) is better than 60%. The corresponding reduction in power delay product is better than 75%.

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.

Carbon Nanotube Field Effect Transistors (CNFETs) are considered to be an ideal choice for implementation of Multi-valued logic circuits, as by using CNFETs multiple thresholds can be obtained by altering the dimensions of the carbon nanotube. Implementation of various CNFET based Ternary Arithmetic circuits like Adders and Multipliers is extensively researched upon. The existing design for a CNFET based Multiplier is based on the classical Wallace approach which uses 3:1 Multiplexers along with Unary operators of Ternary logic. In this paper, design of a novel low power Single-Trit Multiplier and a Three-Trit Multiplier is proposed which uses a 2:1 Multiplexer based design approach. This design shows considerable improvement in terms of power consumption. From the Hspice simulation results, it is noted that the proposed Single-Trit Multiplier design results in up to 99% reduction in Power consumption, 56% reduction in Delay and 99.8% reduction in Power-Delay Product (PDP) when compared to an existing Single-Trit Multiplier. Proposed Three-Trit Multiplier results in savings in power consumption up to 98.2% and 98. 5% reduction in PDP when compared to Three-Trit Multiplier design in the existing literature.

The quantum cellular automata (QCA) paradigm offers an ultra-low-power approach for realizing nanocomputing circuits at the molecular level, offering high parallelism capabilities. This study introduces a coplanar and energy-efficient implementation of the approximate binary discrete cosine transform (BinDCT) module using QCA technology. The proposed BinDCT module integrates various sequential and combinatorial submodules, including multiplexers (MUXs), demultiplexers (DeMUXs), parallel-in-parallel-out right-shift registers (PIPO-RSRs), ripple carry adders (RCAs), and ripple borrow subtractors (RBSs). Each submodule is systematically designed following the standard single-layer design principles, which are crucial for maximizing circuit performance, enhancing reliability, and minimizing power dissipation. Extensive simulations were conducted to validate the logic operation and energy dissipation of each submodule. The simulation results demonstrate a significant reduction in power dissipation- up to and an improvement in circuit area efficiency by compared to previous QCA implementations.

This paper presents a fully programmable 3-D graphics processor using unified shaders for mobile environment. In the system level, we adopted dual-core, dual-issue VLIW, and multithreading methods to utilize instruction, data, and task level parallelism in the graphics applications. In the shader core level, a novel IEEE-754 compliant 4-D vector inner product arithmetic unit and a configurable texture cache are proposed. Using these methods, the proposed processor achieves 143 Mvertices/s and 2.3 Gtexels/s consuming the power of 367 mW. The evaluation shows significant performance and power-delay product benefits. For real graphics applications, test results indicate 2.07 times improvement in performance and 34% reduction in power-delay product compared to previous mobile 3-D graphics processors. The proposed 3-D graphics processor is implemented in 4.5× 4.52 mm using 0.18 μm CMOS technology.

This study delves into the computational aspects of ternary logic and the use of carbon nanotube field-effect transistors (CNTFETs) to develop an energy-efficient and robust ternary multiplier (TMUL). Leveraging the exceptional qualities of CNTFETs, such as balanced electron and hole mobility and easy modulation of threshold voltage, the research aims to achieve the desired designs. An innovative design method is employed, recommending a reduced count of logic gates for achieving necessary logic levels. These gates are then utilized to manage the activation and deactivation of the primary transistors within the TMUL cell to convey the intended logics to the outputs. Moreover, the suggested design is focused on a single-V DD , enhancing compatibility with the goals of a multi-valued logic platform. The proposed circuit is validated using Synopsis HSPICE simulator and Stanford’s standard 32-nm CNTFET model file. Comparative analysis with existing TMUL designs demonstrates a 25.43% decrease in average power consumption, a 42.24% reduction in power-delay product (PDP), and a 24.69% decrease in energy-delay product (EDP). The design undergoes thorough simulations under various conditions including load variations and process, voltage, and temperature (PVT) fluctuations to confirm its reliability and robustness.

We demonstrate over 40% CMOS performance gain with minimal process changes by lowering the operating temperature from 100degC to -50degC. For the same performance, the lower temperature operation delivers a 60% reduction in power-delay product at a reduced supply voltage. Coupled with recent advances in liquid cooling techniques, our results suggest that sub-ambient temperature operation is an attractive option for high performance and energy-efficient CMOS.

In mobile and portable wireless devices, it is important to have low power dissipation so as to maximize battery life. As the overall power dissipation of a device is dominated by the radio frequency (RF) front end rather than the digital circuit, low-power RF front end design has become a very hot topic in both research and implementation. In this paper, we propose a design method to minimize the power dissipation of a RF front end. Specifically, given the overall specifications of gain, linearity and noise figure of a front end, we derive the optimal specification for each building block of the RF front end such that the overall power dissipation is minimized. By using a specific example of a front end consisting of a couple of cascaded circuit blocks using 90nm CMOS technology, we demonstrate that significant reduction in power dissipation can be achieved using the proposed design method.

This paper reports design of a voltage controlled oscillator (VCO) for low power consumption and generation of variable centre frequencies. The current starved technique is used for design of VCO. In normal current starved VCO circuits the centre frequency remains fixed, but here the circuit is designed for generating different centre frequencies, which makes the VCO more versatile. It can generate more frequencies with better resolution. The centre frequency and power dissipation both depend on the number of stages which is selectable. Power dissipation of VCO is estimated based on mathematical modelling and compared with simulation results. Extensive simulations along with performance evaluation of VCO is done to check output frequency and power dissipation. Best simulation results obtained on Tanner EDA tool show that centre frequency can be varied from 3.04 to 9.76 MHz through stage selection. Also, a reduction in power dissipation is obtained from 330 mW to 210 mW through stage selection.