Ultra-Low Power Rectangular Field Programmable Analogue Arrays For Biomedical Applications

The work concerns the problem of switching processes in VLSI technology, reprogrammable analog arrays technology, and nanotechnology. Informatics is a discipline of science exploring the laws of processes of coding, processing, storing and transferring information or data. The movement and processing of Information is indissolubly connected with the switching of states of Structures carrying the data. In general, the changes of structure state can be forced through the changes of carried data parameters with unchanged structure configuration, through the switching of structure configuration or switching of the structure conformation. Switching is exhibited in different technologies by different basic elements (basic Structures or building blocks) and specified operations performed on them in order to obtain the object or product with desirable properties including also the dynamic changes of those properties. Dealing in turn with so different cases as VLSI Structures, FPAA (Field Programmable Analog Array) Structures and nanostructures, it is possible to notice, that the common feature takes a stand in solving the tasks related with them, rely on choice of certain basic elements critical for structure behavior as e.g. multicon-ductor transmission lines (MTL), configurations of FPAA substructures or whole FPAA systems, molecule conformations, and it is operated on them analyzing the internal switching processes. The design of interconnects in a high-speed integrated circuits and systems requires analysis and computer simulation based on interconnects models in the form of coupled, multiconductor transmission lines. The fundamental parameters for matrix description (or modeling, simulation and design) of MTL include the capacitance matrices. Precisely, these are the matrices per-unit of length, the capacitance coefficients matrix called Maxwell matrix of MTL and the two-terminal capacitance matrix. If the two-terminal matrix is known, the Maxwell matrix used for MTL switching characteristics estimation, can be computed from the two-terminal matrix. In the work, two methods of determination of the Maxwell matrix from measurements are presented: passive, indirect measurements and measurements with active separation. The measurements were performed basing on fabricated VLSI test structures named ST2 and AF4. The measurement results arę complemented with the accuracy analysis. Scaling of structures is conformed to fast switching, high-speed integrated YLSI/ULSI integrated circuits design. In case when the geometrical dimensions decrease, multiconductor interconnections between parts of a system become strongly coupled MTL, which in switching moments have to be recharged with smali geometry devices. In the work the method and numerical computations of scaled (in geometrical sense) MTL for its energetical characterization is presented. This can be used for proper design of MTL geometrical parameters in a YLSI/ULSI structures working with a high-speed switching. The results of measurements of the switching delay in the scaled in dimensions VLSI gates, are also included. Poor matching of the switched MTL reveals with reflections extending the time of switching and can be source of switching noises. The method of so called diagonal matching is presented in the work. The time of switching in the high-speed planar VLSI structures (driver and receiver gates connected via the long microstrip line) depends on dielectric properties of substrate under the signal and ground microstrip lines. Most important for fast switching is recharging of dielectric in the presence of the dielectric absorption phenomenon. In the work, the model of dielectric absorption and its identification algorithm based on the experimental data is presented. This model can be used for simulation of switching transients in the interconnections of different length for given technology, taking into account the dielectric absorption. Nowadays, it is apparent that many designs are evolving towards mixed-signal systems. In these kind of circuits in CMOS technology, the analog part of a system and an interface are composed frequently basing on switched capacitor (SC) technology and in the newest solution basing on field programmable analog arrays. There are two main weak points in fast switching of reconfigurable FPAA: firstly, the time of download of the configuration from supporting program or EEPROM memory with the time of transients in a FPAA chip when the download is finished and the chip undertakes its function, and secondly, for recently accessible FPAAs, there is no possibility of switching its parameters values and a part of active structure on-the-fly (during FPAA operation). In the work, the solution of fast switching of the part of working FPAA for adaptive operation is presented. The solution is based on external control of one or few CAB (Configur-able Analog Błock) in the working FPAA. The solution of the download time problem in FPAA chip operating in continuous time fashion is based on parallelization of the FPAAs and "hiding" of the download time and time of transients after download. Finally, the applications of the modified, fast switched FPAAs systems for adaptive and predictive control with possible application in the microreactors control have been presented. In the nanonetworks, an information is transferred through the state of moving molecules. In a short-distance communication (inside the closed area determined by the borders of nano-process) the state of the signaling molecules is forced through the binding via hydrogen or covalent bonds of another molecul or through the interaction of the environment's parameters.These processes in biological nanonetworks are performed in the signal transduction cascades and the same procedures are applied in the nanotechnical system of informatics. We considred these process with emphasis on the fusion of cascades. In general, these interactions lead to the switching of conformations of the molecule. In the work, we focused on biocompatible nanostructure introducing the standard, formal description of molecular structures , methodology of modeling and simulation of the conformation changes, and hierarchical description of nanonetworks useful in the switching conformation studies. The simulation methodologies based on the dynamic programming, Monte Carlo and Nascent Protein Folding algorithms are investigated. Moreover, nanotechnological, two-stage production processes based on the "gluey matrix" concept are discussed.

ABSTRACTA novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The programmability of the proposed DPCCII is achieved using three‐bit MOS R‐2R ladder current division network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is 72.3 mW from 1 V voltage supply. A second‐order programmable universal filter is realized using the proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS technology model under balanced supply voltage of ±0.5 V. Copyright © 2012 John Wiley & Sons, Ltd.

A Comparative Analysis of Continuous-and Discrete-Time Field Programmable Analogue Arrays

Although chaotic signals are considered to have great potential applications in radar and communication engineering, their broadband spectrum makes it difficult to design an applicable amplifier or an attenuator for amplitude conditioning. Moreover, the transformation between a unipolar signal and a bipolar signal is often required. In this paper, a more intelligent hardware implementation based on field programmable analog array (FPAA) is constructed for chaotic systems with complete amplitude control. Firstly, two chaotic systems with complete amplitude control are introduced, one of which has the property of offset boosting with total amplitude control, while the other has offset boosting and a parameter for partial control. Both cases can achieve complete amplitude control including amplitude rescaling and offset boosting. Secondly, linear synchronization is established based on the special structure of chaotic system. Finally, experimental circuits are constructed on an FPAA where the predicted amplitude control is realized through only two independent configurable analog module (CAM) gain values.

This paper deals with the design of very low frequency continuous time filters based on Operational Transconductance Amplifiers (OTAs). Design techniques for both high-performance OTAs and large capacitors are presented. Very small transconductance OTAs with low noise levels and small harmonic distortion components are discussed. Large capacitors are implemented by using impedance scalers based on current mirrors. Design strategies and simulated results for a sixth order 1 Hz lowpass filter are presented.

Analog signal processing (ASP) can be used to decrease energy consumption by several orders of magnitude over completely digital applications. Low-power field programmable analog arrays (FPAA) have been previously used by analog designers to decrease energy consumption. Combining ASP with an FPAA, energy consumption of these systems can be further reduced. For ASP to be most functional, it must achieve rail-to-rail operation to maintain a high dynamic range. This work strives to further reduce power consumption in reconfigurable analog circuitry by presenting a novel data converter that utilizes ASP and rail-to-rail operation. Rail-to-Rail operation is achieved in the data converter with the use of an operational amplifier presented in this work. This efficient yet elementary data converter has been fabricated in a 0.5$\mu$m standard CMOS process. Additionally, this work looks deeper into the challenges of students working remotely, how MATLAB can be used to create circuit design tools, and how these developmental tools can be used by circuit design students.

A CMOS Gm-C filter based on operational trans-conductance amplifiers (OTAs) with low power and tuning ability for biomedical applications is proposed in this paper. The OTA works in the weak inversion region. The transconductance can be tuned by changing the bias current. A fourth-order Butterworth LC ladder Gm-C bandpass filter is implemented by 0.18 μm CMOS process. The supply voltage of the OTA-C filter can be as low as 0.65 V for minimum power dissipation. The power consumption is 61 nW for a sinusoidal input signal of 300 Hz 100 mVPP and 1 V supply voltage and total harmonic distortion is −50.23 dB. The active area is 0.04 mm2.

This paper proposes novel grounded and floating high order series and parallel immittance simulators using operational transconductance amplifiers (OTAs) and operational amplifiers (OAs) with a finite gain–bandwidth (GB) product. They are composed of active devices (OTAs and OAs) and resistances, and are suitable for monolithic implementation in either CMOS or bipolar technologies. They also realize both positive and negative high order immittances. The circuit characteristics can be electronically tuned by adjusting the transconductances of OTAs and the GB products of OAs. Any transfer functions are realizable using the proposed simulators. Two examples are shown, together with simulation results.

This paper discusses design constraints for low distortion Operational Transconductance Amplifiers (OTAs) on integrated analog front ends. It also compares traditional OTA topologies and proposes a new OTA showing significant reduction on distortion for wideband applications, the comparison is presented on a 0.35μm CMOS process. The proposed OTA is designed for on-chip analog front ends for radiation gamma detectors on a 130nm CMOS process.

This work thoroughly investigates and analyses a two-stage Miller-compensated operational transconductance amplifier (OTA) that can be used in the analog front-end (AFE) block of the sensor interface circuit required for the sweat test analyzer to diagnose a life-threatening genetic disease named cystic fibrosis (CF). In doing so, the OTA has been designed and implemented using 45 nm process technology in the cadence simulation framework. Being an essential component in sensor interface circuits, the OTA has to achieve high gain, good transient and frequency response, as well as improved stability, and hence, its design has to meet several specs such as gain-bandwidth product (GBW), slew rate, phase margin, and power dissipation. However, due to increased short-channel effects, the design of OTA using 45 nm process technology is quite challenging. Therefore, a careful design process has been conducted to reduce these short-channel effects. Detailed AC, transient, and stability analyses have been performed along with tweaking the dimensions (channel length and width), the bias voltages and currents and the Miller-compensated capacitance ensures the optimization of the OTA demanded by its application in pre-amplification stages of the sweat-based CF diagnosis. The results obtained in cadence simulation runs for the proposed OTA show excellent promise to realize an AFE used for CF diagnosis with reduced chip size while maintaining accuracy and performance.

SUMMARY This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 μm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closedloop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/ √ Hz, current consumption of 14 μA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter’s building block for low power design. The filter’s single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signalto-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 μW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 μm CMOS process.

In this paper, we propose a three-port circulator circuit based on operational transconductance amplifiers (OTAs) that features a resistorless topology, categorizing it as a type-A circulator. The behavior of the proposed structure is analyzed in the presence of OTA nonidealities, with corresponding mathematical formulations presented. The functionality of the circuit is verified through SPICE simulations using 180[Formula: see text]nm CMOS technology parameters. We also examine the circuit’s performance across various process corners, as well as under supply and temperature variations, finding that the port behavior remains consistent. Additionally, the impact of process variation is assessed through Monte Carlo simulations comprising 100 runs, revealing that the circuit exhibits minimal sensitivity, with the mean frequency at port 2 being 1.006[Formula: see text]MHz and a standard deviation of 493[Formula: see text]Hz. The linearity of the proposed circuit is evaluated, showing a total harmonic distortion (THD) variation of less than 2%.

A simple scheme is presented for realizing four standard second-order transfer functions, i.e. low-pass, high-pass, bandpass, and band-elimination. The system is implemented using only operational transconductance amplifiers (OTAs) and capacitors. The resulting circuit has the attractive feature of wide-range electronic tuning of pole frequency, bandwidth, and pole <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> . These parameters may also be programmed digitally. The OTA-C filter achieves excellent sensitivity performance and is suitable for monolithic IC implementation.

This paper reports on a Field Programmable Analog Array (FPAA) for high-frequency continuous-time analog filters. A rapid-prototyping hardware is presented, which implements a unique hexagonal topology of 55 tunable OTAs for reconfigurable instantiation of Gm-C filters in a 0.13 mum CMOS technology. It is the first analog array to achieve a bandwidth, which allows processing of intermediate frequencies used in communication systems. The maximum power dissipation is 70 mW at 1.2 V supply. The intuitive chip structure allows direct mapping of Gm-C filter schematics with up to 7 independent nodes, immediate download to the hardware, and evaluation of the working prototype.

This paper presents a realization of voltage-mode and current-mode active-only biquad circuits with a two-integrator loop-structure. The circuits are constructed solely with operational amplifiers (OAs) and operational transconductance amplifiers (OTAs). The biquad circuits can realize the multiple circuit transfer functions, and the circuit parameters can be tuned orthogonally through adjusting the transconductance gains of the OTAs. Also, these biquad circuits enjoy very low sensitivities with respect to the circuit active elements. Some examples are given together with simulated results by PSPICE. The circuit configurations are very suitable for implementation on both bipolar and CMOS technologies.